Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
More filters
TL;DR: In this article, the authors proposed an entirely redesigned framework of bandlimited signal reconstruction for the time encoding machine (TEM) introduced by Lazar and Toth, which can be implemented exactly in discrete time with multiplications that are all reduced to scaling by signed powers of two.
Abstract: We propose an entirely redesigned framework of bandlimited signal reconstruction for the time encoding machine (TEM) introduced by Lazar and Toth. As the encoding part of TEM consists in obtaining integral values of a bandlimited input over known time intervals, it theoretically amounts to applying a known linear operator on the input. We then approach the general question of signal reconstruction by pseudo-inversion of this operator. We perform this task numerically and iteratively using projections onto convex sets (POCS). The algorithm can be implemented exactly in discrete time with multiplications that are all reduced to scaling by signed powers of two, thanks to the use of relaxation coefficients. Meanwhile, the algorithm achieves a rate of convergence similar to that of Lazar and Toth. For real-time processing, we propose an approximate time-varying FIR implementation, which avoids the splitting of the input into blocks. We finally propose some preliminary semi-convergence analysis of the algorithm under data noise.
5 citations
01 Jan 2011
TL;DR: A third order system is chosen to establish stable operation over 24KHz Signal Bandwidth with an Oversampling Ratio of 64 and a sampling frequency of 3.72 M Hz.
Abstract: We present design considerations for low pass sigma delta modulators for audio applications. A third order system is chosen to establish stable operation over 24KHz Signal Bandwidth with an Oversampling Ratio of 64 and a sampling frequency of 3.72 M Hz. A binary quantizer is used to maintain linearity in the modulator. Behavioural Modeling of the system shows signal-to-noise-and-distortion-ratio (SNDR) of 84.8 dB and Dynamic Range of 81dB. A CIFB topology is used and design is implemented in 0.25 micron CMOS Technology.
5 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...The equations for updating the state and computing the output of the loop filter are (2) (3) This formulation is sufficiently general to encompass all singlequantizer modulators which employ linear loop filters [8]....
[...]
TL;DR: The influence to the dynamic range when performing dynamic receive beamforming on recorded delta-sigma modulated bit-stream sequences is demonstrated and is comparable with state-of-the-art feedforward type multi-bit designs.
Abstract: Fully digitized 2D ultrasound transducer arrays require one ADC per channel with a beamforming architecture consuming low power. We give design considerations for per-channel digitization and beamforming, and present the design and measurements of a continuous time delta-sigma modulator (CTDSM) for cardiac ultrasound applications. By integrating a mixer into the modulator frontend, the phase and frequency of the input signal can be shifted, thereby enabling both improved conversion efficiency and narrowband beamforming. To minimize the power consumption, we propose an optimization methodology using a simulated annealing framework combined with a C++ simulator solving linear electrical networks. The 3rd order single-bit feedback type modulator, implemented in a 65 nm CMOS process, achieves an SNR/SNDR of 67.8/67.4 dB across 1 MHz bandwidth consuming 131 [Formula: see text] of power. The achieved figure of merit of 34.2 fJ/step is comparable with state-of-the-art feedforward type multi-bit designs. We further demonstrate the influence to the dynamic range when performing dynamic receive beamforming on recorded delta-sigma modulated bit-stream sequences.
5 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...The current most power efficient CTDMS are all of feedforward type designs, plagued by typically 10 dB peaking in their signal transfer function close to the in-band region [15], thus sacrificing dynamic range....
[...]
...Instead of a discrete time implementation of the modulator, we choose continuous time because of its inherent anti-aliasing filter property, low die area and potential for low power [10], [15]....
[...]
30 Mar 2015
TL;DR: It is shown how the enhanced unscented Kalman filter is used to perform an in situ non-ideality estimation and subsequent calibration of a manufactured chip, bringing the modulator back into its designed performance range.
Abstract: In this paper, an enhanced unscented Kalman filter is used for the estimation of non-idealities in sigma-delta modulators. As sigma-delta modulator based analog-to-digital converters are known to be prone to performance degradation from many circuit non-idealities, testing and selection of the manufactured chips as well as post-correction procedures are required to ensure a reliable performance. In contrast to most state-of-the art techniques, the proposed estimator is capable of simultaneously tracking a large set of non-ideal parameters with high accuracy and in a very short offline time within the range of microseconds. Three possible implementations are proposed and it is shown how the technique is used to perform an in situ non-ideality estimation and subsequent calibration of a manufactured chip, bringing the modulator back into its designed performance range. It is further demonstrated that the estimator can reliably detect the non-idealities over a wide range when intentionally degrading the performance of the chip by manually sweeping its trimming parameters. The presented hardware measurement results prove that the proposed technique is practically applicable to the test and/or calibration of sigma-delta data converters.
5 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...In order to apply the estimator to a DT modulator, its filter can readily be modeled as it was shown several times before [1], [2]....
[...]
...2395611 relatively robust and—in principle—simple to build, non-idealities in the filter and feedback part of the modulator have to be considered to avoid performance degradations [1]–[4]....
[...]
01 Oct 2017
TL;DR: The proposed sigma-delta (ΣΔ) modulator of near infrared charging with Bluetooth antenna of wake-up receiver is presented for internet of things (IoT) wireless charging application.
Abstract: The proposed sigma-delta (ΣΔ) modulator of near infrared charging with Bluetooth antenna of wake-up receiver is presented for internet of things (IoT) wireless charging application Continuous-time quadrature bandpass sigma-delta modulator control strategy has been adopted in state-of-the-art wireless power transfer (WPT) applications to meet power demand with the highest efficiency against coupling and load variations The multi-charging modulator has built in near-infrared laser-driven (NIRLD) might be a promising wireless electrical power source
5 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...In the CIFF topology, the output of each opamp has lower output swing than the chain of integrators with distribute feedback (CIFB) [13]....
[...]
References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations