Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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TL;DR: In this paper, the authors used column-level oversampling delta-sigma ADCs to suppress the spatial and temporal noise in a CMOS image sensor (CIS) and demonstrated that using a longer-length column bias transistor, both the fixed pattern noise (FPN) and the temporal noise can be suppressed.
Abstract: This paper presents methodologies for suppressing the spatial and the temporal noise in a CMOS image sensor (CIS). First of all, it demonstrates by using a longer-length column bias transistor, both the fixed pattern noise (FPN) and temporal noise can be suppressed. Meantime, it employs column-level oversampling delta-sigma ADCs to suppress temporal noise as well as to facilitate the realization of the thermal compensation of dark signal non-uniformity (DSNU). In addition, the image pixels are re-configured as temperature sensors with inaccuracies within ±0.65 °C, between −20 and 80 °C. If the dark current and its non-uniformities are caused by thermal gradients, the obtained in-pixel thermal information can be employed to compensate for the measured dark current by 95 % and DSNU, up to 13 %. All the column-level 13 bit 2nd-order incremental delta-sigma ADCs are measured with SNR around 65 dB and INL around 1.5 LSB, when tested with a −8 dB input signal and sampling at 2 MHz with an oversampling ratio (OSR) of 128, when the full scale voltage is 2 Vp-p. The 4T Pinned Photodiode (PPD) CIS is measured to have a temporal noise of $34~\mu \text{V}$ rms (with an OSR of 128, or, an input referred temporal noise of 0.5 e− rms, with a conversion gain, CG, of $73~\mu \text{V}/ \text{e}^{-}$ ), a column gain FPN of 0.06 %, a dynamic range (DR) of 92 dB (with OSR = 512), as well as a linearity of 1 %. It has a measured DSNU of 3.2 %, after the thermal compensation using the in-pixel temperature sensors, a dark current of 290 pA/cm2 and 15 pA/cm2, measured at 60 °C, before and after the thermal compensation, respectively.
5 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...7 shows the schematic of the 2nd order incremental delta-sigma ADC used in this design, in reference to [8] below....
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...Being a fully differential design, it has a folded cascode architecture and needs a switched capacitor common mode feedback (CMFB) [8]....
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01 Nov 2018
TL;DR: A novel highly-digital BPΔ ΣTDC for IF applications is proposed and an all-digital realization of a TM lossless discrete integrator (LDI)- based resonator is presented that achieves high-speed time-mode signal processing without the limitations imposed by switched-capacitor (SC) circuit techniques.
Abstract: Aggressive scaling of CMOS technology in sub-100 nm process motivates the replacement of voltage or current-mode signal processing with time-mode approaches which uses digital circuits to perform signal processing. As the time difference between two signals is independent of the amplitude of either signal, intuitively, a time-mode (TM) signal representation is believed to be more compatible with newer CMOS processes that operate at lower power supply levels. It is the objective of TM circuit architects and researchers to identify new circuit architectures that can perform basic signal processing operations such as adding, subtracting, multiplications, etc. At the heart of these efforts is the need to identify TM circuits that perform such operation at high performance levels; levels that equal or exceed those of voltage-mode (VM) circuits at similar power levels.
In the first phase of this thesis, an intensive review of the literature is presented. The review includes ΔΣ analog-to-digital converter (ADC) specifications and all the major developments in the area of TMΔΣ converters in the last decade. Then we present a rigorous comparison between discrete-time TM circuits and continuous-time VM circuits to identify gaps that need to be filled. As a first contribution, we provide an analytical expression for the noise operation of both a VM and TM PMOS-NMOS transistor stack, leading to the expression of the peak-SNR of both architectures. The proposed noise theory is applied to different CMOS process and compared in Spectre. In addition, we provide IC implementations with measurement results to verify the analysis finding.
Then, as a second contribution, we propose new TM building blocks and extensions to some old ones that alleviate the challenges imposed by modern CMOS technologies, without affecting the performance metrics. The first challenge is the need for half-period delay and full-period delay unit for TM circuits; the second challenge is the need for TM circuits to perform basic arithmetic operations (i.e., addition or subtraction) in wide linear range; and the third challenge is how to realize negative feedback in time-domain and process signals at higher frequency around intermediate frequency (IF).
As a third contribution, an all-digital realization of a TM lossless discrete integrator (LDI)- based resonator is presented. The resonator is constructed by new TM building blocks in a negative feedback configuration. This achieves high-speed time-mode signal processing without the limitations imposed by switched-capacitor (SC) circuit techniques such as the matching of capacitors to realize precise signal gains. Instead, circuit precision is realized using an adaptive delay circuit to adjust the loop delay in a wide range of sampling frequencies. The operation of the TM LDI-based resonator is validated with transistor-level simulations and compared with system-level in Simulink/MATLAB.
Finally, we propose a novel highly-digital BPΔ ΣTDC for IF applications. It first introduces the system architecture of the proposed design and presents the expected performance metrics. The BPΔΣTDC is able to shape the quantization noise in a negative feedback configuration, and it does not require any complex calibration circuit to compensate for timing errors. In addition, for the very first time in TMSP, a direct feed-forward compensation is utilized in the TDC to achieve high signal-to-noise and distortion ratio (SNDR). We demonstrate the proposed TDC in an IBM 130 nm CMOS process, while operating from a supply voltage as low as 1.2 V. A continuous sampling frequency range from 4 MHz to 42.8 MHz is achieved to digitize an input signal that is centered at one-quarter of sampling frequency. It achieves a 39.5 dB peak SNDR over a 0.2 MHz signal bandwidth at maximum sampling frequency fs =42.8 MS/s while consuming lower than 5 mW power. Furthermore, we identify future directions in TM circuit design and high-order realization of BPΔ ΣTDC for research.
5 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...In order to achieve this, two topologies have been presented in (Pavan et al., 2017) that are suitable for this application, using a single-loop and a MASH architecture....
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...This action has come to be known in the ΔΣ modulator literature as noise-shaping (Pavan et al., 2017; Jose et al., 2011; Kozak et al., 2003), where the quantization noise introduced by the quantizer is pushed or shaped away in frequency from the signal band....
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DOI•
01 Jan 2014
TL;DR: In this paper, the authors present a Table of Contents and Table of Table of Contents (table of contents): Table of contents: Table of contents: table of contents.
Abstract: ....................................................................................................iii TABLE OF CONTENTS......................................................................................v LIST OF TABLES.............................................................................................vii LIST OF FIGURES..........................................................................................ix CHAPTER
5 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...Therefore, when calculating the output signal power, , y P of the ΣΔM, the value of K is selected as the ΣΔM’s effective gain, Keff, which is the value of K that minimizes the power, , e P of the quantization noise [8]....
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...However, the Cascaded topologies require tighter constraints on circuit specifications and mismatch than single- loop s [8]....
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TL;DR: This study presents an ultra-low-power, small-size, 1-bit, single-ended, and switched-capacitor SC delta-sigma analog-to-digital converter ADC for wireless acoustic sensor nodes that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low-power consumption.
Abstract: This study presents an ultra-low-power, small-size, 1-bit, single-ended, and switched-capacitor SC delta-sigma analog-to-digital converter ADC for wireless acoustic sensor nodes. This wireless sensor node has a delta-sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low-power consumption. The chip area of the delta-sigma ADC is dominated by the capacitor; therefore, a novel common-mode CM controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08mm2 in a 130-nm CMOS process. The conventional operational transconductance amplifiers OTAs are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4-MHz sampling frequency and 0.7-V power supply voltage, the delta-sigma ADC achieves a 55.8-dB signal-to-noise-plus-distortion ratio SNDR and a 298-fJ/step figure-of-merit FOM in a signal bandwidth of 25kHz, while consuming only 7.5µW of power. Copyright © 2015 John Wiley & Sons, Ltd.
5 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...FOM is generally used to evaluate the performance of the delta-sigma ADC, and it is defined by [19,27],...
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...In addition, the separate capacitor greatly increases the chip area, so sharing capacitor [19] is utilized...
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...Ideally, it can obtain an 80-dB SNR for a sufficient margin [19]....
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...5; the coefficients were decided based on a MATLAB simulation [19], as shown in Figure 3....
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...Figure 7 presents the adopted clock generator circuit [19], which consists of logic gates....
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03 Dec 2010
TL;DR: This work improves performance of A/D converters even more, by combining this optimal family of SDM with iterative methods.
Abstract: In this paper a new iterative method is used to convert analog signals to digital (A/D) using sigma delta modulator (SDM) If intelligent reconstruction technique is used for decoding, either signals with higher bandwidth can be digitized or simpler circuitry can be utilized An optimal family of SDM has recently been devised in order to improve performance of A/D converters In this work, we improve performance of A/D converters even more, by combining this optimal family of SDM with iterative methods
5 citations
References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations