Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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27 May 2007
TL;DR: An online estimation of the real values of continuous-time delta-sigma modulators based on an unscented Kalman filter is presented: no linearization of the strongly nonlinear system equation has to be performed as a deterministic set of sampling points is used for the estimation.
Abstract: Circuit nonidealities such as real opamp behavior, coefficient mismatch, excess loop delay or jitter are known to drastically reduce the performance of continuous-time delta-sigma modulators. In this paper, the first step toward a successful correction and therewith compensation of these errors is presented: an online estimation of their real values based on an unscented Kalman filter. Contrary to the classical approach, which makes use of an extended Kalman filter, no linearization of the strongly nonlinear system equation has to be performed as a deterministic set of sampling points is used for the estimation. Therewith, the estimation performance is drastically increased, while the calculation effort still remains the same.
5 citations
TL;DR: This paper introduces an architecture to enhance coding efficiency (CE) and bandwidth of the delta sigma modulator transmitters using a low pass envelope delta s Sigma modulator (LPEDSM) to reduce the quantization noise and to improve the CE.
Abstract: This paper introduces an architecture to enhance coding efficiency (CE) and bandwidth of the delta sigma modulator transmitters. In this architecture a low pass envelope delta sigma modulator (LPEDSM) is used instead of traditional cartesian low pass delta sigma modulator (LPDSM) to reduce the quantization noise and to improve the CE. Simulation results show that for an Uplink long term evolution (LTE) signal with 1.4 MHz bandwidth, 7.8-dB peak to average power ratio (PAPR), and an oversampling ratio (OSR) of 32, the CE for the polar LPEDSM transmitter is equal to 42 % in compare to 9.7 % CE for cartesian LPDSM transmitter. In the next step, a quantization noise reduction loop with in-band quantization noise filtering are implemented in this architecture. By using this combined technique for an Uplink LTE signal with 1.4 MHz bandwidth, with the same PAPR and OSR of 32, the CE is improved from 42 to 59.33 % with 40 dB signal to noise and distortion ratio.
5 citations
12 Dec 2011
TL;DR: In this paper, a systematic method for the design of feed forward ΣΔ interfaces is proposed, and simulations show that the utilizing the proposed method, feed forward method and the traditional multiple feedback structures have almost the same peak SQNRs when a compensator pole is added to the feed forward structure.
Abstract: High order ΣΔ interface is a practical choice for high resolution MEMS sensors. Previous researches are mainly about the determination of the coefficients of multiple feedback ΣΔ interfaces. In the work presented here, a systematic method for the design of feed forward ΣΔ interface is proposed. Simulations show that the utilizing the proposed method, feed forward method and the traditional multiple feedback structures have almost the same peak SQNRs when a compensator pole is added to the feed forward structure. However, feed forward structure has many advantages, so the proposed method is a promising alternative method for the multiple feedback structure.
5 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...The models of third order, fourth order and fifth order electromechanical ΣΔ modulators for simulation are shown as figure 13, figure 14 and figure 15 respectively....
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...Sigma-Delta MEMS is suitable for many applications, such as inertial navigation systems, unmanned aerial vehicles, earthquake prediction and seismic exploration for oil and mineral resources....
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...Ⅰ INTRODUCTION Sigma-Delta (ΣΔ) modulation is a widely used method for low speed high resolution A/D conversion, which improves the effective resolution of a coarse quantizer by embedding it in an oversampled negative feedback loop [1]....
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TL;DR: Transistor-level simulations on an audio band modulator and a 10-MHz bandwidth modulator are given, verifying the high immunity of the proposed circuit to clock jitter, ISI, and aliasing while attaining a power efficiency up to 7.4 fJ/conversion step.
Abstract: Recent progress in continuous-time (CT) Delta–Sigma modulators (DSMs) research has shown that applying a passive RC low-pass filter (LPF) in the feedback path can significantly improve the power efficiency of a CT DSM. On the other hand, to achieve high performance, a CT DSM faces the adverse effects of clock jitter, intersymbol interference (ISI), or degradation of antialiasing ability. These challenges are extremely difficult to tackle simultaneously without consuming excessive power. This paper proposes a Gm-C DSM with a combined RC and switched-capacitor LPF frontend stage to achieve a high performance against aliasing, clock jitter, and ISI simultaneously while having an extremely low power consumption. Transistor-level simulations on an audio band modulator and a 10-MHz bandwidth modulator are given, verifying the high immunity of the proposed circuit to clock jitter, ISI, and aliasing while attaining a power efficiency up to 7.4 fJ/conversion step.
5 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...With the method used in [26], the in-band jitter-induced noise power is calculated as Pj ≈ (σ t τ )2 e− Ts τ...
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TL;DR: The proposed design methodology is applied to the design of a phase-to-digital converter in a 40-nm CMOS process, which is used to digitize the output of a thermal-diffusivity temperature sensor, achieving ± 0.2° phase inaccuracy and sensor-limited resolution within a 500-Hz bandwidth.
Abstract: VCO-based phase-domain $\Sigma \Delta $ modulators employ the combination of a voltage-controlled-oscillator (VCO) and an up/down counter to replace the analog loop filter used in conventional $\Sigma \Delta $ modulators. Thanks to this highly digital architecture, they can be quite compact, and are expected to shrink even further with CMOS scaling. This paper describes the analysis and design of such converters. Trade-offs between design parameters and the impact of non-idealities, such as finite counter length and VCO non-linearity, are assessed through both theoretical analysis and behavioral simulations. The proposed design methodology is applied to the design of a phase-to-digital converter in a 40-nm CMOS process, which is used to digitize the output of a thermal-diffusivity temperature sensor, achieving ± 0.2° ( $3\sigma $ ) phase inaccuracy from -40 to 125 °C and a sensor-limited resolution of 57 m° (RMS) within a 500-Hz bandwidth. Measurements on the prototype agree quite well with theoretical predictions, thus demonstrating the validity of the proposed design methodology.
5 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...It is well known that first order modulators are affected by idle tones if the input signal does not have enough white noise content [18] [21]....
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...The wrap-around can be avoided by limiting the counter’s output swing, which is analogous to limiting the output swing of integrators in a regular modulator to avoid amplifier saturation [21]....
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References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations