Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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Patent•
27 Jul 2016TL;DR: In this article, a noise-shaping signed digital-to-analog (S2A) converter is described, which selectively enables a first sequence of unit elements of a plurality of units of a D2A converter to convert a signed digital code to the output of a phase/frequency detector and charge pump.
Abstract: A noise-shaping signed digital-to-analog converter is described A method includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a signed digital code to a plurality of analog signals in response to a plurality of control signals Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements The method includes generating the plurality of control signals based on a pointer, a magnitude of the signed digital code, and a sign of the signed digital code The method may include combining the plurality of analog signals with an output of a phase/frequency detector and charge pump in a phase-locked loop The signed digital code may be an error signal based on a predetermined divide ratio of the phase-locked loop
5 citations
28 Apr 2015
TL;DR: In this paper, the authors proposed an interleaved boost DC-DC converter for renewable energy applications, which uses a simplified delta-sigma modulation to control the pulse generator.
Abstract: It is generally accepted that interleaving techniques are efficient at reducing the input/output ripples and increasing the power output of boost converters operating in the critical conduction mode. Pulse width modulation (PWM) is commonly used to produce the switching pattern. But this technique causes large switching noise peaks at a multiple number of the carrier frequency. This paper proposes Interleaved Boost DC-DC converter suitable for renewable energy applications. The proposed converter utilises a simplified delta-sigma modulation to control the pulse generator. A thorough and effective analysis of the converter is carried out in order to achieve the required system stability and to improve the dynamic performance. The output response characteristics obtained by this method is very much improved compared to the conventional PWM method of control. Simulation results are presented to illustrate the advantages of the proposed scheme. All the advantages of interleaving, such as higher efficiency and reduced ripple for voltage/current, are also maintained in the proposed converter.
5 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...An equivalent discrete time model for the SDM can be obtained by using the following difference equation[13]:...
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...DM is an analog-to-digital modulation technique used mainly for a wide variety of applications, including digital telephony over the internet, digital wireless and 4 generation mobile communications [13]....
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TL;DR: A novel reduced-code technique is presented for the static linearity test of split-capacitor SAR ADCs based on the on-chip generation and measurement of the major carrier transitions of the input digital-to-analog converter of the converter.
Abstract: Reduced-code techniques for an analog-to-digital converter (ADC) static linearity test have the potential to drastically reduce the number of necessary measurements for a complete static linearity characterization. These techniques take advantage of the repetitive operation of certain families of converters such as pipelines, successive-approximation registers (SARs), cyclic, etc. In this paper, we present a novel reduced-code technique for the static linearity test of split-capacitor SAR ADCs based on the on-chip generation and measurement of the major carrier transitions of the input digital-to-analog converter of the converter. The proposed test method does not require a test stimulus, and we show that the necessary measurements can be easily extracted by reconfiguring portions of the SAR into a low-resolution incremental ${\Sigma \Delta }$ converter. The proposed technique is validated with both behavioral and electrical simulations of a 10-bit SAR ADC in a 65-nm CMOS technology.
5 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...On the other hand, oversampling ADCs are more prone to gain and offset errors, and it has been proved that the incremental modulation is inherently more robust to complex non-linear effects such as idle tone generation and dead zones [19]....
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09 Aug 2021
TL;DR: In this article, a power-efficient linearization technique based on bulk-modulation for the voltage-to-frequency conversion characteristic of the ring voltage-controlled oscillator (VCO), which can be easily adopted in VCO-based ADCs to achieve high resolution.
Abstract: This paper presents a power-efficient linearization technique based on bulk-modulation for the voltage-to-frequency conversion characteristic of the ring voltage-controlled oscillator (VCO), which can be easily adopted in VCO-based analog-to-digital converters (ADCs) to achieve high resolution. A bulk-control voltage generator is utilized to modulate the threshold voltages of the VCO input transistors. Combined with the conventional gate-control scheme, the nonlinearity of the VCO can be reduced effectively. A second-order sigma-delta ADC with proposed linearized VCO is implemented in 0.18μm CMOS technology to verify the effectiveness. Simulation results show the nonlinearity of the VCO drops from 10% to 2% and the total distortion can be reduced by 19dB through bulk-modulation compared with conventional VCO.
5 citations
References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations