Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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TL;DR: A low-power reference voltage buffer with fast load transient response that can be used to drive capacitive loads, based on an improved replica-biasing source follower structure that combines the high precision of the closed loop and the high bandwidth of the open loop, and it meets the requirements of high precision, fastload transient response for a sigma-delta modulator.
Abstract: This paper presents a low-power reference voltage buffer with fast load transient response that can be used to drive capacitive loads. The circuit is based on an improved replica-biasing source follower structure that combines the high precision of the closed loop and the high bandwidth of the open loop, and it meets the requirements of high precision, fast load transient response for a sigma-delta modulator. The proposed circuit is implemented in 0.18 μm CMOS technology provided by Semiconductor Manufacturing International Corp. (SMIC). The reference voltage buffer is combined with a sigma-delta modulator. The result shows that when the load capacitor is 10 pF, the settle time is 134 ns, the quiescent current is 81.5 μA, and the chip area is 117 μm × 220μm.
4 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...An analog-to-Digital Converter (ADC) is usually applied to convert a continuous analog signal to a discrete digital signal [1]....
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01 Sep 2020
TL;DR: A delta-sigma modulation (DSM) technique implemented in the field-programmable gate array (FPGA) for DU which is further interfaced with a power amplifier in RRU through feeder cable is presented.
Abstract: This paper explores multi-band all-digital transmitter architecture suitable for 5G next-generation radio access network (NG-RAN). In NG-RAN, most of the radio frequency (RF) layer functions are moved to a distributed unit (DU) in the digital domain so that a low cost and small size remote radio unit (RRU) can be developed. This paper presents a delta-sigma modulation (DSM) technique implemented in the field-programmable gate array (FPGA) for DU which is further interfaced with a power amplifier in RRU through feeder cable. A single bit 1st and $2^{\mathrm{n}\mathrm{d}}$ order low-pass DSM is implemented in FPGA of DU. An IQ sequencing block and high-speed serializer multiplexer are used to digitally up-convert the baseband signals to the different carrier frequencies in DU. The proposed scheme is validated with transmission of long-term evolution (LTE) signal of 5 MHz bandwidth for single as well as multi-band operation. The performance of the transmitter is measured in terms of signal to noise distortion ratio (SNDR) and error vector magnitude (EVM).
4 citations
01 Jan 2016
TL;DR: This chapter discusses asymptotes and extracts recent improvement rates in the area of low-power, high-performance A/D conversion using figure-of-merit plots presented in CHIPS 2020 using new survey data collected over the years 2011–2015.
Abstract: By updating the figure-of-merit plots presented in CHIPS 2020 using new survey data collected over the years 2011–2015, this chapter discusses asymptotes and extracts recent improvement rates in the area of low-power, high-performance A/D conversion. Moreover, five years after the writing of CHIPS 2020, the developments in current architectures will be re-iterated, and the emerging concept of analog-to-information conversion will be discussed.
4 citations
Proceedings Article•
17 Mar 2009TL;DR: The architecture of an all-digital transmitter with radio frequency (RF) output targeting FPGA devices due to their reconfigurability and reprogrammability is presented and designed using VHDL design entry and ready for download on the target FPG a.
Abstract: The term software defined radio (SDR) is usually used to refer to a radio transceiver in which its key parameters are defined in software and having its fundamental aspects reconfigurable by upgrading that software. SDR architecture has been proposed as a solution to support multiple wireless standards on a single platform. In this paper, we present the architecture of an all-digital transmitter with radio frequency (RF) output targeting FPGA devices due to their reconfigurability and reprogrammability. The all-digital transmitter directly synthesizes RF signal in the digital domain using Low Pass Delta Sigma Modulation (LPDSM). This eliminates the need for most of the analog and RF components. The all digital transmitter consists of one Cascaded Integrator Comb (CIC) filter, one LPDSM modulator and Digital Upconverter (DUC). The binary output waveform from the RF-ΔΣ modulator is centered at 800MHz with bit rate of 1.6 Gbps. The proposed architecture has been simulated to prove the idea and test its performance. Finally, the proposed architecture is designed using VHDL design entry and ready for download on the target FPGA.
4 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...This is equivalent to OSR of 25 and effective number of bits (ENOB) of 9 [11]....
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...The used architecture of the loop filter is a cascade of resonators with distributed feedback coefficients (CRFB) [11]....
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...This is the main factor affecting the quality of the delta sigma conversion process [11]....
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TL;DR: A detailed derivation of the digital cancelation filters for continuous-time cascaded architectures is presented in order to achieve maximum signal-to-noise ratio together with optimal anti-aliasing performance.
Abstract: This paper deals with a systematic approach to the synthesis of continuous-time cascaded sigma---delta modulators. Based on a system-theoretical model, a detailed derivation of the digital cancelation filters for continuous-time cascaded architectures is presented in order to achieve maximum signal-to-noise ratio together with optimal anti-aliasing performance. By using the same model, an exact equation for the performance loss of any cascaded architecture is derived. The latter is due to the scaling for stability and given relative to an ideal high-pass filter of the overall modulator order. Finally, an analytical calculation of optimal scaling coefficients in between the stages is performed, resulting in a limited search-space for these coefficients. Theoretical results are verified by simulations.
4 citations
References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations