Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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02 Apr 2019
TL;DR: Results show that increasing thevalue of (n) by one bit in digital word, the value of SQNR increases by 6 Decibels (dB), which is higher than the theoretical value as the number of bits increased in the digital word.
Abstract: This paper considers the effects of the quantization error and Signal Quantization Noise Ratio (SQNR) on the performance of an Analog Digital Converter of the sine signal using the Truncating method to the nearest integer bit. This Truncating method assigns each sample of the sine signal to the quantization level below it. By using MATLAB program, the experimental SQNRTruncating was always lower than the theoretical value as the number of bits increased in the digital word. This was expected because truncating the data leads to less accurate quantization of the signal and a lower SQNR. StatGraphics software was used to analyze simple regressions of the quantization error, and compare between Standard Deviation and Mean Absolute Deviation of the quantization error. StatGraph Plus program has been used to analyze the effect of the correlation coefficient statistic for truncating. Analysis Regression - Linear model using the StatGraph Plus program has been performed, then analysis of the effect of the statistic correlation coefficient and the equation of the regression line of dependent value (SQNR)Truncating on the independent value ‘number of bits (n)’ is accomplished. Results show that increasing the value of (n) by one bit in digital word, the value of SQNR increases by 6 Decibels (dB).
4 citations
TL;DR: The paper presents the first AlN-on-Si oscillator platform with ź 0.5ppm frequency stability over temperature ranges from -40°C to 85°C, and runs on 1.8V supply in 32nm CMOS.
4 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...Using Delta-Sigma toolbox in MATLAB [21], peak SQNR of 80 dB requires OSR of 64 for 2nd order 1 bit modulator and for 3rd order CIC decimator (CIC order1⁄4analog modulator orderþ1), the Ncycles needed is specified to be 64*31⁄4192 cycles....
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...To achieve TCXO stability, a BJT-based temperature sensor is combined with a switched capacitor sigmadelta Σ∆ modulator [21] as shown in Fig....
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...13 is chosen to implement the modulator for faster conversion time, lower integrator's capacitor ratios, and better linearity [21]....
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...Using Delta-Sigma toolbox in MATLAB [21], peak SQNR of 80 dB requires OSR of 64 for 2nd order 1 bit modulator and for 3rd order CIC decimator (CIC order¼analog modulator orderþ1), the Ncycles needed is specified to be 64*3¼192 cycles....
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29 Apr 2010
TL;DR: In this article, the authors present iterative algorithms which efficiently compute an optimized subset of equiprobable input symbols that achieves near capacity on a large asymmetric discrete memoryless channel (DMC).
Abstract: We present iterative algorithms which efficiently compute an optimized subset of equiprobable input symbols that achieves near-capacity on a large asymmetric discrete memoryless channel (DMC). The optimized subset defines a delay-free channel-adapted inner code which can be combined with a standard code. The introduction of a dense data structure renders it possible to apply channel-adaptive coding to 2-bit quantized MIMO systems, which exhibit a very large output set. The coding approach is shown to be robust to imperfect channel state information (CSI). Finally, we present a binary index switching algorithm that minimizes the BER by optimizing the mapping from code bits to input symbols.
4 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...UltraWideband (UWB) communications, the use of low resolution analog-to-digital converters (ADCs) simplifies the circuit design and saves power as well as chip area [1]....
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14 May 2012
TL;DR: This paper describes the architecture and principles of operation of sigma-delta Sigma-Delta time-to-digital converters for high-speed I/O interface circuit test applications, and proposes two methods to improve the overall TDC linearity: a data-weighted averaging algorithm and a self-calibration method that measures delay values using a ring oscillator circuit.
Abstract: This paper describes the architecture (circuit design) and principles of operation of sigma-delta Sigma-Delta time-to-digital converters (TDC) for high-speed I/O interface circuit test applications, they offer good accuracy with short test times. In particular, we describe multi-bit $\Sigma\Delta$ TDC architectures for fast testing. However, mismatches among delay cells in delay lines degrade the linearity there. Then we propose two methods to improve the overall TDC linearity: a data-weighted averaging algorithm, and a self-calibration method that measures delay values using a ring oscillator circuit. Our MATLAB and Spectre simulation results demonstrate the effectiveness of these approaches.
4 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...This is because the input signal of TDC is ”time” while that of ADC is ”voltage”....
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...However, the multi-bit ΣΔ TDC may suffer from mismatches among delay units, which degrades the TDC linearity (which is similar to the multi-bit ΣΔ ADC [7])....
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...We close this section by remarking that the similar selfcalibration technique is used in ΣΔ ADC [8], [9], where the nonlinearity measurement of the multi-bit DAC inside the ΣΔ ADC modulator is difficult....
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...Since the integrator output INTout is digitized with an array of comparators (a flash ADC without an encoder), its output Dout is in a thermometer code format....
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...We use an array of comparators (a flash ADC without an encoder) whose outputs are connected to the selection signals of the multiplexers....
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01 Nov 2006
TL;DR: A new design of a decimation filter for sigma-delta AD converter with adjustable filter order for obtaining 12-20 bit output resolution is described in this paper.
Abstract: A new design of a decimation filter for sigma-delta AD converter with adjustable filter order for obtaining 12-20 bit output resolution is described in this paper The design is implemented by 018 mum 6-metal CMOS technology, with chip area 14times14 mm2 The decimation filter can be considered as a standard module in ASIC library and be applied to inputs with 10~18 bit resolution at low frequency
4 citations
References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations