Understanding Delta-Sigma Data Converters
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Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...Typically, at least 90 dB attenuation is required to efficiently prevent noise aliasing in a second-order ΣΔ modulator with OSR = 64 (Schreier & Temes, 2005)....
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...In this paper, we will only consider a second-order single-bit modulator because it offers reasonably good linearity and stability performances, yet at much lower hardware expenses than multi-bit and higher-order modulators (Schreier & Temes, 2005)....
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...For a second-order modulator, the OSR should typically be higher than 80 (Schreier & Temes, 2005)....
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...This can be attained by a second-order ΣΔ modulator with OSR ≥ 64 (Schreier & Temes, 2005)....
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...First because the modulator (namely the analogue parts of it) is specifically designed for an oversampling clock rate and a change in its operating frequency may impact its performances such as, for instance, through integrators saturation (Schreier & Temes, 2005)....
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4 citations
4 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...5) the delta sigma modulator will have to decrease the noise quantification level and so improving the signal to quantization noise ratio (SQNR) of the ADC [6]....
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...Thus, the principle of operation of a Sigma-Delta modulator is characterized by the oversampling concept [6], [7] ,[8]....
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...The Sigma-Delta convertor is composed by two blocks, a sigma –delta Modulator that will convert the analog input to a one bit digital output and a decimation filter that will increase the resolution of the final output data [6], [7]....
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References
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