scispace - formally typeset
Search or ask a question
Book

Understanding Delta-Sigma Data Converters

TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

Content maybe subject to copyright    Report

Citations
More filters
Journal ArticleDOI
Ge Binjie1, Wang Xin'an1, Zhang Xing1, Feng Xiaoxing1, Wang Qingqin1 
TL;DR: The quantization noise leakage of the first stage in a MASH21 sigma–delta modulator is analyzed and the results show that the finite DC gain of the opamp is the main reason for noise leakage, and finite GBW and SR only generate harmonic distortion.
Abstract: The quantization noise leakage of the first stage in a MASH21 sigma–delta modulator is analyzed. The results show that the finite DC gain of the opamp is the main reason for noise leakage, and finite GBW and SR only generate harmonic distortion. The relationship between DC gain and leakage is modeled and conclusions on design criteria are reached. As an example, a MASH21 modulator for a digital audio application is realized. This modulator, fabricated in an 0.18 μm mixed signal process, achieves an SNDR of 91 dB with 1.8 V supply, which verifies the analysis and design criteria.

4 citations

Proceedings ArticleDOI
22 May 2016
TL;DR: A new loop filter topology with four poles and two zeros is proposed and compared to existing loop filters reveals that the proposed loop filter can yield more energy-efficient noise-shaping SAR ADCs than the ones seen in the literature today.
Abstract: Oversampling and noise-shaping have in recent years been introduced to SAR ADCs to improve the conversion accuracy. Similar to delta-sigma ADCs, this is done by means of a feedback loop containing a loop filter. In this paper, the high-level design of this loop filter is discussed, and important differences to classical delta-sigma loop filter design are pointed out. Among others, it is found that the poles of the noise transfer function, and not only the zeros, play a significant role on the conversion accuracy. Based on this, a new loop filter topology with four poles and two zeros is proposed and compared to existing loop filters. This reveals that the proposed loop filter can yield more energy-efficient noise-shaping SAR ADCs than the ones seen in the literature today.

4 citations

Journal ArticleDOI
TL;DR: A new smart and compact system dedicated to control the output sampling frequency of an analogue-to-digital converters (ADC) based on single-bit sigma-delta (ΣΔ) modulator that dramatically improves the spectral analysis capabilities of power network analysers (power meters) by adjusting the ADC’s sampling frequency to the input signal's fundamental frequency.
Abstract: This paper presents a new smart and compact system dedicated to control the output sampling frequency of an analogue-to-digital converters (ADC) based on single-bit sigma-delta (ΣΔ) modulator. This system dramatically improves the spectral analysis capabilities of power network analysers (power meters) by adjusting the ADC’s sampling frequency to the input signal’s fundamental frequency with a few parts per million accuracy. The trade-off between straightforwardness and performance that motivated the choice of the ADC’s architecture are preliminary discussed. It particularly comes along with design considerations of an ultra-steep direct-form FIR that is optimised in terms of size and operating speed. Thanks to compact standard VHDL language description, the architecture of the proposed system is particularly suitable for application-specific integrated circuit (ASIC) implementation-oriented low-power and low-cost power meter applications. Field programmable gate array (FPGA) prototyping and exper...

4 citations


Cites background or methods from "Understanding Delta-Sigma Data Conv..."

  • ...Typically, at least 90 dB attenuation is required to efficiently prevent noise aliasing in a second-order ΣΔ modulator with OSR = 64 (Schreier & Temes, 2005)....

    [...]

  • ...In this paper, we will only consider a second-order single-bit modulator because it offers reasonably good linearity and stability performances, yet at much lower hardware expenses than multi-bit and higher-order modulators (Schreier & Temes, 2005)....

    [...]

  • ...For a second-order modulator, the OSR should typically be higher than 80 (Schreier & Temes, 2005)....

    [...]

  • ...This can be attained by a second-order ΣΔ modulator with OSR ≥ 64 (Schreier & Temes, 2005)....

    [...]

  • ...First because the modulator (namely the analogue parts of it) is specifically designed for an oversampling clock rate and a change in its operating frequency may impact its performances such as, for instance, through integrators saturation (Schreier & Temes, 2005)....

    [...]

Book ChapterDOI
01 Jan 2018
TL;DR: A dynamic zoom ADC for audio applications that achieves 109-dB DR, 106-dB SNR, and 103- dB SNDR in a 20-kHz bandwidth, while dissipating 1.12 mW and occupying only 0.16 mm2 in 0-μm CMOS translates to state-of-the-art energy and area efficiency.
Abstract: This paper presents a dynamic zoom ADC for audio applications. It achieves 109-dB DR, 106-dB SNR, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating 1.12 mW and occupying only 0.16 mm2 in 0.16-μm CMOS. This translates to state-of-the-art energy and area efficiency. In this paper, the system- and circuit-level design of the ADC will be presented.

4 citations

Proceedings ArticleDOI
12 Mar 2014
TL;DR: The development of a digital tool dedicated for the test and the simulation of a reading system for neutron detection is presented and the different results of simulation related to the input designed parameters of the readout system are presented.
Abstract: The development of a digital tool dedicated for the test and the simulation of a reading system for neutron detection is presented. This study takes place in the framework of the I_SMART * European project. This system will have to work in harsh environment in terms of temperature and radiations what makes necessary the development of specifications for operation and reliability of the components and also the investigation of margins of interplay of the components. The specifications of the implemented tool are presented here with the different results of simulation related to the input designed parameters of the readout system.

4 citations


Cites background or methods from "Understanding Delta-Sigma Data Conv..."

  • ...5) the delta sigma modulator will have to decrease the noise quantification level and so improving the signal to quantization noise ratio (SQNR) of the ADC [6]....

    [...]

  • ...Thus, the principle of operation of a Sigma-Delta modulator is characterized by the oversampling concept [6], [7] ,[8]....

    [...]

  • ...The Sigma-Delta convertor is composed by two blocks, a sigma –delta Modulator that will convert the analog input to a one bit digital output and a decimation filter that will increase the resolution of the final output data [6], [7]....

    [...]

References
More filters
Journal ArticleDOI
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

399 citations

Journal ArticleDOI
James C. Candy1
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.

342 citations

Journal ArticleDOI
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

284 citations

Book ChapterDOI
James C. Candy1, O. Benjamin1
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.

255 citations

Journal ArticleDOI
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >

211 citations