Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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10 Jun 2011
TL;DR: It is shown that clever design of the NTF and the STF of the multi-stage QΣΔM offers both straightforward reconfigurability and robustness against converter implementation mismatches.
Abstract: In this article, the design and analysis of sophisticated multi-band quadrature ΣΔ modulators (QΣΔM) are addressed, offering a high-performance and easily-reconfigurable solution for the analog-to-digital (A/D) interface of cognitive radio receivers. Based on spectrum sensing information, the multi-band principle stemming from multi-stage converter implementation enables multiple reconfigurable noise transfer function (NTF) notches for efficient quantization noise shaping. Also mirror-frequency-rejecting signal transfer function (STF) design is proposed for multi-stage QΣΔM, which implements part of the receiver selectivity and offers also robustness against certain circuit implementation nonidealities. More specifically, we concentrate here on the so-called in-phase / quadrature (I/Q) imbalance problem, being an unavoidable problem in quadrature circuits and thus also in QΣΔMs. An analytical closed-form model is derived for a two-stage QΣΔM under implementation nonidealities, realizing multi-band noise shaping with first-order building blocks. Stemming from this analysis, it is shown that clever design of the NTF and the STF of the multi-stage QΣΔM offers both straightforward reconfigurability and robustness against converter implementation mismatches.
4 citations
01 Jan 2007
TL;DR: In this article, the effects of synchronous demodulation and electrostatic quadrature compensation performed with a dc voltage on the final zero-rate output (ZRO) of a vibratory microgyroscope are studied.
Abstract: In this paper, issues related to the zero-rate output (ZRO) of a vibratory microgyroscope are studied. Different sources of the ZRO are discussed and how the effect of each source can be minimized and their stability improved is described. The effects of synchronous demodulation and electrostatic quadrature compensation performed with a dc voltage on the final ZRO are analyzed. Ways to implement the control loop for electrostatic quadrature compensation performed with a dc voltage are de- scribed, concentrating on a case where the compensation voltage is generated with a digital-to-analog converter and the controller is digital. In particular, extending the resolution with tech- niques is studied. The experimental work shows the feasibility of the implemented quadrature compensation loop and analyzes the ZRO sources of one particular gyroscope implementation. How to perform the ZRO measurements in such a way that the various sources can be distinguished from each other is also described.
4 citations
TL;DR: A double sampling technique is proposed for a digital-to-analog converter feedback circuit to reduce the effect of the reference voltage, reduce the amplifier requirements, and obtain low-power consumption for portable electrocardiogram applications.
Abstract: This study proposes a subsystem consisting of an analog buffer and a single-ended input to a fully differential ΔΣ modulator to obtain low-power consumption for portable electrocardiogram applications. With the proposed subsystem, the need for an inverting amplifier is avoided, and low-power consumption is achieved. The ΔΣ modulator with a second order, 1bit, and cascade of integrators feedforward structure consumes a low power, in which an inverting and a non-inverting path implement a single-ended input to fully-differential signals. A double sampling technique is proposed for a digital-to-analog converter feedback circuit to reduce the effect of the reference voltage, reduce the amplifier requirements, and obtain low-power consumption. Input-bias and output-bias transistors working in the weak-inversion region are implemented to obtain an extremely large swing for the analog buffer. At a supply voltage of 1.2V, signal bandwidth of 250Hz, and sampling frequency of 128kHz, the measurement results show that the modulator with a buffer achieves a 77dB peak signal-to-noise-distortion ratio, an effective-number-of-bits of 12.5 bits, an 83dB dynamic range, and a figure-of-merit of 156dB. The total chip size is approximately 0.28mm2 with a standard 0.13µm Complementary Metal-Oxide-Silicon CMOS process. Copyright © 2016 John Wiley & Sons, Ltd.
4 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...The measured FOM1 Copyright © 2016 John Wiley & Sons, Ltd. Int....
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...To achieve low-power consumption and reduce the noise of the reference common-mode voltage, this study also proposes using a double sampling technique [19] for a DAC feedback circuit in the modulator....
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...Its input part (dashed box) consists of an inverting path and a non-inverting path, which are utilized to implement the single input to a fully-differential structure [19]....
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...FOM1 [19] and FOM2 [23, 24], used for comparison, are defined as follows: FOM1 ¼ DRþ 10log BandwidthPower ; (5) FOM2 ¼ Power 2 Bandwidth 2 SNDR-1:76ð Þ=6:02 : (6) According to the measurement results in Tables III and IV, an FOM1 of 156 dB and an FOM2 of 4.18 pJ/step with a signal bandwidth of 250Hz, as well as an FOM1 of 154 dB and an FOM2 of 2.49 pJ/step with the signal bandwidth of 500Hz, are achieved in this study....
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...As shown in Figure 4, a double sampling technique [19] for the DAC feedback circuit is proposed in this study, and Figure 5 presents the DAC feedback controlling circuit and its feedback controlling signals....
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18 Jul 2010
TL;DR: A sensor array readout approach where synchronous sigma-delta converters are interfacing each sensing point and whose outputs are concurrently downsampled by dedicated hardware for decimation processing is proposed.
Abstract: An increasing amount of sensor applications require multiple data acquisition with high resolution in truly parallel fashion. This requirement is particularly useful in the field of Nanotechnology where concurrent acquisition is required to understand the correlation between weak stochastic events. In this paper, we will propose a sensor array readout approach where synchronous sigma-delta converters are interfacing each sensing point and whose outputs are concurrently downsampled by dedicated hardware for decimation processing. The approach shows the following advantages: on the one hand the sigma-delta conversion ensures high resolution and linearity (>12 bits), on the other, the 1-bit output allows easier routing access to the array. The approach is particularly useful in the presence of very low signals where direct raster-mode switching access to the array would compromise the signal-to-noise ratio of the readout process. As a proof of this concept, the approach is applied to an array of lipid bilayer membranes (BLMs) permitting to acquire and display single molecule event data by means of a PC-based graphical user interface (GUI).
4 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...As a proof of this concept, a real application was presented for singlemolecule events on parallel single ion-channels recording....
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...We are also grateful to the “Fondazione Cassa dei Risparmi di Forlì” for its support....
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01 Aug 2017
TL;DR: A single-ended scheme which uses double sampling and time interleaving to achieve a performance comparable to that of differential circuits, which requires only half the complexity and reduced power dissipation compared to fully-or pseudo-differential circuits.
Abstract: Pseudo-differential circuits approximate the performance of fully-differential structures, while allowing single-ended operation of the two half stages in the circuit This requires duplication of the circuitry, with accurate symmetry needed between the two halves to cancel common-mode noise This paper proposes a single-ended scheme which uses double sampling and time interleaving to achieve a performance comparable to that of differential circuits It requires only half the complexity and reduced power dissipation compared to fully-or pseudo-differential circuits
4 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...3 illustrates the implementation of a second-order delta-sigma modulator MOD2 [2]....
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...3b. shows the implementation of MOD2 with the P2D architecture, using a simplified version of the integrator of Fig....
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...3a shows the circuit of a conventional single-ended second-order modulator MOD2....
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...As an illustration, a comparison of the two circuit structures and their output spectra for the MOD2 ADC leads to the following conclusions: Noise: In a differential structure, under ideal conditions all symmetric noises are cancelled....
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...However the feed-forward capacitor Cf in the MOD2 of Fig, 3b cancels the signal in the loop filter, reducing the effects of finite gain and slew rate [2]....
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References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations