Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
More filters
TL;DR: A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.
Abstract: This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.
235 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...However, even considering an ideal circuit implementation, the result in (4) can not be achieved in practice due to the scaling required in the loop filter coefficients [13]....
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...A good example is the describing-function based model proposed in [23] and used in the well-known Schreier’s Delta-Sigma MATLAB Toolbox [13], [24]....
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...for the synthesis of Ms [7], [13], [98]–[100]....
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...The latter term M will be used in this paper, although both terms are widely used [13]....
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...To this purpose, the well-known Schreier’s MATLAB Delta-Sigma toolbox [13],...
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TL;DR: In this article, an integrated digital controller for dc-dc switchmode power supplies (SMPS) used in portable applications is introduced, which has very low power consumption, fast dynamic response, and can operate at programmable constant switching frequencies exceeding 10 MHz.
Abstract: An integrated digital controller for dc-dc switch-mode power supplies (SMPS) used in portable applications is introduced. The controller has very low power consumption, fast dynamic response, and can operate at programmable constant switching frequencies exceeding 10 MHz. To achieve these characteristics, three novel functional blocks, a digital pulse-width modulator based on second-order sigma-delta concept (Sigma-Delta DPWM), dual-clocking mode compensator, and nonlinear analog-to-digital converter are combined. In steady state, to minimize power consumption, the controller is clocked at a frequency lower than SMPS switching frequency. During transients the clock rate is increased to the switching frequency improving transient response. The controller integrated circuit (IC) is fabricated in a standard 0.18-mum process and tested with a 750-mW buck converter prototype. Experimental results show the controller current consumption of 55 muA/MHz and verify closed-loop operation at programmable switching frequencies up to 12.3 MHz. Simulation results indicating that this architecture can potentially support operation at switching frequencies beyond 100 MHz are also presented.
218 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...It utilizes a second-order – modulator to achieve high effective resolution and operation without noise related problems, typically existing in first-order – DPWM implementations [21]....
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...In the later case, the resolution of DPWM, i.e., its time quantization steps, is constrained by finite propagation time of ring oscillator delay cells....
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24 Jun 2007
TL;DR: This paper considers the extreme case of only 1-bit ADC for each receive signal component, and shows that QPSK is, up to the second order, the best among all distributions with independent components in the low signal-to-noise ratio regime.
Abstract: We study the performance of multi-input multi-output (MIMO) channels with coarsely quantized outputs in the low signal-to-noise ratio (SNR) regime, where the channel is perfectly known at the receiver. This analysis is of interest in the context of ultra-wideband (UWB) communications from two aspects. First the available power is spread over such a large frequency band, that the power spectral density is extremely low and thus the SNR is low. Second the analog-to-digital converters (ADCs) for such high bandwidth signals should be low-resolution, in order to reduce their cost and power consumption. In this paper we consider the extreme case of only 1-bit ADC for each receive signal component. We compute the mutual information up to second order in the SNR and study the impact of quantization. We show that, up to first order in SNR, the mutual information of the 1-bit quantized system degrades only by a factor of 2/pi compared to the system with infinite resolution independent of the actual MIMO channel realization. With channel state information (CSI) only at receiver, we show that QPSK is, up to the second order, the best among all distributions with independent components. We also elaborate on the ergodic capacity under this scheme in a Rayleigh flat-fading environment.
218 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...On the other hand, the degradation of the bandwidth-efficiency related with UWB communication can be partly compensated with the use of multiple antennas, at the cost of some additional processing complexity....
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TL;DR: In this article, a two-stage pipeline ADC architecture with a large first-stage resolution, enabled with the help of a SAR-based sub-ADC, is presented, achieving an ENOB of 104b at Nyquist and a figure-of-merit of 52 f J/conversion-step.
Abstract: Successive approximation register (SAR) ADC architectures are popular for achieving high energy efficiency but they suffer from resolution and speed limitations On the other hand pipeline ADC architectures can achieve high resolution and speed but have lower energy-efficiency and are more complex We pro pose a two-stage pipeline ADC architecture with a large first-stage resolution, enabled with the help of a SAR-based sub-ADC The prototype 12b 50 MS/s ADC achieves an ENOB of 104b at Nyquist, and a figure-of-merit of 52 f J/conversion-step The ADC achieves low-power, high-resolution and high-speed operation without calibration The ADC is fabricated in 65 nm and 90 nm CMOS and occupies a core area of only 016 mm2
201 citations
17 May 2004
TL;DR: It is shown that sigma-delta (/spl Sigma//spl Delta/) algorithms can be used effectively to quantize finite frame expansions for R/sup d/.
Abstract: It is shown that sigma-delta (/spl Sigma//spl Delta/) algorithms can be used effectively to quantize finite frame expansions for R/sup d/. Error estimates for various quantized frame expansions are derived, and, in particular, it is shown that /spl Sigma//spl Delta/ quantizers outperform the standard PCM schemes.
199 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
..., see [31], [38], is to assume that the state variables in the scheme (13) are independent and identically distributed uniform random variables with zero mean and variance ....
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References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations