Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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TL;DR: This study proposes a CMOS MEMS audio transducer implemented by combining a silicon condenser microphone with analog front-end audio codec circuits that can operate without any charge pump circuits, which overcomes the problem of requiring a high bias voltage.
Abstract: This study proposes a CMOS MEMS audio transducer implemented by combining a silicon condenser microphone with analog front-end audio codec circuits. The proposed CMOS MEMS audio transducer is attractive because the sensor and all the circuits are robustly and compactly integrated. The overall size of the proposed device is much smaller than traditional electrets-condenser microphones (ECMs). Another innovation of the proposed CMOS MEMS audio transducer is that it can operate without any charge pump circuits, which overcomes the problem of requiring a high bias voltage. Measurement results confirm the correct functions and performance of the proposed CMOS MEMS audio transducer. The area of the proposed CMOS MEMS audio transducer is 1352×1410 μm2 and the FOM of the proposed sigma-delta modulator is 148 dB. The proposed CMOS MEMS audio transducer is suitable for audio devices, such as audio codecs.
4 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...Next, the zero optimization [11] leads to...
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...Researchers have used several different modulators to achieve high resolution, such as multi-loop cascade, multi-bit, high-order single-loop single-bit [11]....
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...To get around the limited capacitor matching in CMOS processes, this study uses dynamic element matching [11] to convert the nonlinearity of the 2-bit DAC into noise....
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...The FOM can be expressed as follows: [11]...
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TL;DR: In this article, a time-mode smart temperature sensor in a standard 180-nm CMOS process, intended for on-chip thermal monitoring applications, has been presented, where a new temperature-to-pulse converter (TPC) is proposed utilising programmable temperature compensation devices.
Abstract: This work presents a time-mode smart temperature sensor in a standard 180 nm CMOS process, intended for on-chip thermal monitoring applications. A new temperature-to-pulse converter (TPC) is proposed utilising programmable temperature compensation devices, where a dual delay-line configuration is adopted, namely sensor and reference delay-lines. The proportional to absolute temperature (PTAT) delay offered by the sensor delay-line has a temperature coefficient (TC) of 720 ppm/°C, whereas almost constant delay possessed by the reference delay-line has a TC of 60 ppm/°C, over 0–100 °C temperature range. The proposed 1st-order $$\Delta \Sigma$$ time-to-digital converter (TDC) serves as the smart sensor readout, where a novel delay-cell is proposed using multipath approach. The projected $$\Delta \Sigma$$ TDC achieves 30 ns full-scale range at 9 ps resolution. The dual delay-line configuration in the TPC and the dynamic element matching in the $$\Delta \Sigma$$ TDC bound the inaccuracy of the proposed smart temperature sensor to ± 0.68 °C. The sensor shows a resolution of 0.03 °C at 0.5 $$\upmu \hbox {s}$$ conversion time.
4 citations
Posted Content•
TL;DR: A new adaptive spiking neuron model that can be abstracted as a low-pass filter that enables faster and better training of spiking networks using back-propagation, without simulating spikes is proposed.
Abstract: The increasing need for compact and low-power computing solutions for machine learning applications has triggered significant interest in energy-efficient neuromorphic systems. However, most of these architectures rely on spiking neural networks, which typically perform poorly compared to their non-spiking counterparts in terms of accuracy. In this paper, we propose a new adaptive spiking neuron model that can be abstracted as a low-pass filter. This abstraction enables faster and better training of spiking networks using back-propagation, without simulating spikes. We show that this model dramatically improves the inference performance of a recurrent neural network and validate it with three complex spatio-temporal learning tasks: the temporal addition task, the temporal copying task, and a spoken-phrase recognition task. We estimate at least 500x higher energy-efficiency using our models on compatible neuromorphic chips in comparison to Cortex-M4, a popular embedded microprocessor.
4 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...e Laplace-domain representation of the noise introduced into the loop, for example by the spike generation mechanism. The loop described by Equation 5 is similar to a continuous-time modulation loop (Pavan et al., 2017) with the key difference being that the output spikes are unipolar. This is valuable because the output of a conventional loop is always active (+1 or 1), whereas the asynchronous model is only active...
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...ar et al. (2019); Schemmel et al. (2012), are potentially more energy-efficient than their digital counterparts but suffer from device mismatch. A feedback loop naturally compensates for such effects (Pavan et al., 2017) but there are many components in the model that lies outside the feedback loop. To study this, we add the effect of mismatch in our simulations by sampling the parameters, p of the mapped SNN: p= p(1...
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01 Jan 2008
4 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...where STF (z) = z−m is a signal transfer function that delays the input signal by m samples, and NTF (z) = (1 − z−1)L is a noise transfer function that contributes to minimization of the quantization noise within the signal band [13]....
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...Alternative converter architectures, such as oversampling delta-sigma (∆Σ) converters, offer resolutions greater than 16-bits [12], require mostly digital circuitry, and compared to Nyquist-rate converters, don’t rely on high precision analog components [13]....
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...∆Σ converter architectures require primarily digital circuitry, and when compared to pipeline converters, they don’t rely on high precision analog components [13, 63]....
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...For a second-order ∆Σ modulator, the signal-to-noise ratio (SNR) is given by [13, 89]...
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...In general, for the L order ∆Σ modulator, L + 1 comb filters are cascaded to sufficiently reduce the out-of-band quantization noise [13]....
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01 May 2017
TL;DR: To remove the DACs from the feedback path and to replace the multi-level signal with a multi-bit one, a Hopfield artificial neural network is used with delta-sigma modulators as neurons and results in a circuit configuration more compact than that of conventional ADCs using the DAC.
Abstract: Conventional analog-to-digital converters (ADCs) with medium or high bit-resolution have a feedback path that connects a tentative digital output with the analog input to obtain a final digital output. Digital-to-analog converters (DACs) are used in the feedback path to generate the multi-level analog signal that is needed to process the feedback signal with the input signal in the analog domain. In this paper, Nyquist and oversampling ADCs using no DACs are presented, and their operations are proved by a behavior-model simulation. To remove the DACs from the feedback path and to replace the multi-level signal with the multi-bit one, a Hopfield artificial neural network is used with delta-sigma modulators as neurons. This new ADC architecture results in a circuit configuration more compact than that of conventional ADCs using the DAC.
4 citations
References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations