Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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Dissertation•
18 Jul 2016
TL;DR: This Master Thesis work aims to design a low power high-resolution Delta-Sigma modulator for ADC in a low-cost standard mixed-mode CMOS technology with benefit of the low-power Class-AB Op.
Abstract: This Master Thesis work aims to design a low power high-resolution Delta-Sigma modulator for ADC in a low-cost standard mixed-mode CMOS technology. For this purpose, a single-bit single loop Delta-Sigma architecture will be selected in order to mitigate distortion issues caused by technology mismatching. Also, the switched capacitor (SC) circuit implementation of the Delta-Sigma modulator will avoid the use of any internal voltage supply bootstrapping for biasing critical switches in favor of extending IC lifetime. The designer will take benefit of the low-power Class-AB Op
3 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...The Walden FOM is given by FOMWalden ≡ P 2 ·BW · 2ENOB (1.4) where P is the static power consumption and the ENOB is the effective number of bits, which is derived from the SNDR expressed in dB, and defined as ENOB ≡ SNDR(dB)− 1.76 6.02 (1.5) The main drawback with respect this FOMs is a bias towards low-power medium resolution designs rather than high resolution, and thus benefits from CMOS technology scaling....
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...3, in can be concluded that in order to get close to the boundary defined by Schreier [26], it is necessary to scale down the static power consumption....
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...The analysis and the implementation of the decimator filter is out the scope of this work, the interested reader may reference [26]....
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...The second FOM is the Schreier FOM which is described as FOMSchreier ≡ SNDR+ 10 log( BW P ) (1.6) This FOM is preferred for comparing high resolution ADCs limited by thermal noise....
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...This outstanding state-of-the-art forseen FOM is achieved by the use of architectural and circuital Lowpower techniques....
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12 Mar 2008
TL;DR: A novel well-proved model for describing the combined error due to clock jitter and quantization noise on the performance of bandpass sigma delta (SigmaDelta) analog to digital converters (ADCs) is built.
Abstract: In this paper, we build a novel well-proved model for describing the combined error due to clock jitter and quantization noise on the performance of bandpass sigma delta (SigmaDelta) analog to digital converters (ADCs). The clock jitter is modeled as a timing variation of the sampling process which follows the characteristic of the Wiener process. Computer simulations as well as theoretical calculations are performed and the two confirm each other. Results show that clock jitter severely degrades the system's performance in terms of achievable signal to noise ratio (SNR). It is also shown that, when the clock jitter becomes more dominant compared to the quantization noise, increasing the oversampling ratio (OSR) and/or the order of SigmaDelta ADCs do not improve the performance significantly.
3 citations
TL;DR: This work proposes a procedure for characterizing and benchmarking the shaping methods forlinearizing a digital-to-analog converter by mismatch noise shaping and provides five graphical figures of merit related to in-band spurious level and noise floor.
Abstract: Linearizing a digital-to-analog converter by mismatch noise shaping is popular particularly in the art of Delta-Sigma converters. This work proposes a procedure for characterizing and benchmarking the shaping methods. The proposed approach provides five graphical figures of merit related to in-band spurious level and noise floor. In our case-studies, we will concentrate on the data-weighted averaging method with low- and bandpass shaping alongside a combination of two-tone suppression methods.
3 citations
TL;DR: In this paper, a low power and area-efficient 3rd-order continuous-time delta-sigma (CT ΔΣ) modulator for LTE/TD-SCDMA digital receivers is presented.
Abstract: This paper presents a low power and area-efficient 3rd-order continuous-time delta-sigma (CT ΔΣ) modulator for LTE/TD-SCDMA digital receivers. In the proposed modulator, the integrators' coefficients are programmable to meet all LTE and TD-SCDMA signal bandwidths and dynamic range requirements. Moreover, to meet both the high performance and low-cost requirements, the proposed analog-to-digital converter (ADC) adopts: a low-cost excess loop delay compensation method, a non-return-to-zero feedback digital-to-analog converter (DAC) which is clocked by low-noise LC phase lock loop, an on-chip tuning scheme to reduce sensitivity to bandwidth variations, and dynamic element matching 9-level DACs. The CT ΔΣ modulator is designed and fabricated in a 0.13 μm 1-poly 6-metal standard CMOS technology and occupies an active area of 0.20 mm2. For all signal bandwidths of LTE/TD-SCDMA standards, the proposed ADC achieves 70---87 dB dynamic range, and 66---84 dB peak SNDR with 8.4---10.2 mW power consumption under 1.5 V power supply.
3 citations
TL;DR: A design method based on curve fitting approximation for uncertain linearized model of the modulator which is simple in principle and practical in application is proposed and results show that the optimal filter has better performance on multiple validations when compared to other modulator filters.
Abstract: Uncertain components in the integrators of 2–1 Sigma–Delta modulators cannot eliminate the first stage quantization noise completely, and the signal-to-noise ratio in analogue-to-digital converters is not reduced perfectly either. In order to solve the matching problem, older filter designs based on convex optimization are mathematically complicated, computationally intensive and not so efficient in application. In this paper, we propose a design method based on curve fitting approximation for uncertain linearized model of the modulator which is simple in principle and practical in application. Simulation results show that the optimal filter has better performance on multiple validations when compared to other modulator filters.
3 citations
References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations