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Understanding Delta-Sigma Data Converters

TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
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Journal ArticleDOI
TL;DR: In this article, a hybrid continuous-time/discrete-time (DT) multi-stage noise shaping (MASH) sigma-delta (ΣΔ) modulator architecture for broadband applications is presented.
Abstract: In this paper, a hybrid continuous-time (CT)/discrete-time (DT) multi-stage noise shaping (MASH) sigma---delta (ΣΔ) modulator architecture for broadband applications is presented. The double-sampling technique is employed in the DT second-stage modulator in order to reduce the power consumption of the overall modulator. Flat and unity signal transfer functions are used in the first- and second-stage modulators, respectively, to relax the output swing of the analog building blocks without influencing the inherent anti-aliasing behavior of the first-stage CT modulator. The proposed structure is insensitive to the amplifier limited dc gain of CT stage and avoids the need of compensation for finite gain-bandwidth induced error in CT loop filter. As a design example, the proposed MASH 2-2 modulator is designed in a 90 nm CMOS technology with 1 V power supply. Circuit level simulation results with HSPICE achieve the maximum SNDR of 74.8 dB and dynamic range of 76.5 dB in 12.5 MHz bandwidth with 17 mW power consumption while operating at 200 MHz sampling rate.

3 citations


Cites background or methods from "Understanding Delta-Sigma Data Conv..."

  • ...These RD modulator topologies circumvent the stability problems related to the high order loops, but, they are sensitive to the quantization noise leakage caused by mismatches between the analog and digital signal processing parts [6]....

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  • ...The optimal value of g to maximize the SNDR is obtained as follows [6]:...

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  • ...For calculating the parameter SNDR, 32768-points FFT is used with a Hann window [6]....

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01 Jan 2016
TL;DR: This dissertation presents an ultra-low power (ULP) phase-domain RX architecture for the Bluetooth Low Energy (BLE) applications and proposes a direct frequency demodulator (DIFDEM) RX, which has a zero-IF architecture and uses minimum possible analog circuitry, which allows it to avoid image issue and achieve low power consumption simultaneously.
Abstract: This dissertation presents an ultra-low power (ULP) phase-domain RX architecture for the Bluetooth Low Energy (BLE) applications. By 2020, there will be up to 10 to 100 billion wireless sensor devices connected to internet-of-things (IoT)[1]. With the increasing demand on prolonging the battery lifetime, the power consumption of the RF transceivers for such applications has been dramatically reduced in the past few years [2][3]. However, the cost of replacing/recharging the batteries will become a bottleneck for massive deployment of the remote wireless sensors. Therefore, continuous innovation on power and supply reduction of the IoT RF transceivers is needed to extend the battery life time or one step further to achieve complete autonomous operation using energy harvesting. A phase-domain single-channel RX, proposed in [4], transforms the analog-I/Q signal processing into digital-phase processing by combining a phase-rotator based phase tracking loop and the sliding-IF architecture. It demonstrates an approximately 40% power reduction compared to the conventional Cartesian RX architecture. However, it still requires multi-phase generation hardware and suffers from the image rejection issue. The proposed direct frequency demodulator (DIFDEM) RX has a zero-IF architecture and uses minimum possible analog circuitry, which allows it to avoid image issue and achieve low power consumption simultaneously. Instead of phase rotator, the DIFDEM RX uses digitally controlled oscillator (DCO) as a feedback element in the phase tracking loop. Further, to meet tight adjacent channel rejection ratio (ACR) and frequency tolerance specifications of the BLE, DIFDEM employs a 3rd-order elliptic filter and an automatic frequency noise cancellation (AFC) loop. Post layout simulation results indicate that DIFDEM RX can achieve -89 dBm sensitivity and -20/-30 dB ACR at 2/3 MHz, while consuming <1700 µA current at 0.85 V supply. It also meets the BLE frequency tolerance specification of ±150 kHz.

3 citations

Proceedings ArticleDOI
15 May 2011
TL;DR: It is shown that this is not the case when a switched capacitor (SC) feedback DAC is used, thereby nullifying one of the principal advantages of continuous-time operation.
Abstract: Continuous-time Delta Sigma Modulators (CTDSM) have “Implicit Anti-Aliasing” - is a commonly heard refrain in the data-converter design community. We show that this is not the case when a switched capacitor (SC) feedback DAC is used, thereby nullifying one of the principal advantages of continuous-time operation. We give an intuitive understanding of this phenomenon, and propose a power efficient circuit technique to improve alias rejection.

3 citations

Patent
01 Jun 2006
TL;DR: In this article, an improved quadrature bandpass ΔΣ converter includes a loop filter, an ADC responsive to the loop filter and a first feedback DAC responsive to ADC; a first summing circuit is responsive to first DAC and an analog input for providing an input to loop filter.
Abstract: An improved quadrature bandpass ΔΣ converter includes a loop filter, an ADC responsive to the loop filter, and a first feedback DAC responsive to the ADC; a first summing circuit is responsive to the first DAC and an analog input for providing an input to the loop filter; a second feedback DAC is responsive to the ADC for providing an input to the loop filter; the loop filter includes a plurality of signal resonators, at least one image resonator, a second summing circuit, and a feed forward circuit connecting at least two of the resonators to the second summing circuit for reducing the quantization noise from the ADC; the image resonator is responsive to the second DAC for reducing the image quantization noise.

3 citations

References
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Journal ArticleDOI
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

399 citations

Journal ArticleDOI
James C. Candy1
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.

342 citations

Journal ArticleDOI
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

284 citations

Book ChapterDOI
James C. Candy1, O. Benjamin1
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.

255 citations

Journal ArticleDOI
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >

211 citations