Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
More filters
TL;DR: A pulse-width-modulation (PWM) technique is proposed for CT cascaded DSMs for on-chip automatic RC time constant tuning, which in turn enables the use of a correlated double sampling (CDS) technique to boost the effective dc gain of the opamp.
3 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...In this paper, a pulse-width-modulation (PWM) technique is proposed for CT cascaded DSMs for on-chip automatic RC time constant tuning, which in turn enables the use of a correlated double sampling (CDS) technique to boost the effective dc gain of the opamp....
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...Anti-aliasing filtering Although the anti-aliasing advantage of continuous-time DSM has been shown to be limited when the opamp finite gain effects is considered [18], if adding the discrete-time nature of the PWM, the anti-aliasing capability of the PWM-tuned CT modulator will degrade further....
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...However, for cascaded CT DSM, the finite GBW induced gain errors dominate the behavior due to the cascaded structures' high sensitivity to it, and the second pole effect can be ignored [8]....
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...A prototype CT cascaded 2-2 DSM operating from a low supply voltage of 0.8 V is designed and fabricated in a 0.18-μm CMOS....
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...However, the RC time constant variation (in case of active-RC circuit implementation, or equivalently the gm/C variation in gm–C implementations) and finite opamp dc gain affect the accuracy of NTF1, leading to imperfect cancellation of the first stage's quantization noise [7,8]....
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Proceedings Article•
01 Dec 2011TL;DR: A novel simulation method and possibility of class S power amplifier for LTE base station is presented and shows 31 % PAE and 2 % EVM.
Abstract: This paper presents novel simulation method and possibility of class S power amplifier for LTE base station. A baseband signal with 9.7 dB Peak-to-Average Power Ratio (PAPR) is used to represent LTE signal, which is about top 12-percent of the PAPR statistics. The channel bandwidth of 10 MHz and carrier frequency of 890.88 MHz is used to represent prearranged LTE service in Korea. A Band-Pass Delta-Sigma Modulator (BPDSM) is used to generate a digital-like signal. A Gallium-Nitride (GaN) based Complementary Voltage Switched Class D (CVSCD) with this digital-like signal is simulated and shows 31 % PAE and 2 % EVM.
3 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...To generate digital-like signal from the modulated RF signal, fourth order BPDSM is used [16]....
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TL;DR: A novel approach for HP cascaded ΔΣ modulator is presented, which attains better dynamic range, stability and achievable SNR than conventional cascade architecture and has the flexibility of using any second-order HP Δ modulator architecture in the first stage.
Abstract: High-pass (HP) delta-sigma (ΔΣ) modulators find utilisation in applications which are sensitive to low-frequency noises because of their complete immunity to these noises (Nguyen in High-pass DS modulator and its application to time-interleaved DS converter, Ecole Nationale Superieur des telecommunications, PhD Dissertation, 2004) Single-stage HP ΔΣ modulator of order-2 has been presented in Nguyen et al (Proceedings of ISCAS, 2006) This paper presents a novel approach for HP cascaded ΔΣ modulator, which attains better dynamic range, stability and achievable SNR than conventional cascade architecture This approach has the flexibility of using any second-order HP ΔΣ modulator architecture in the first stage We have used traditional HP ΔΣ modulator (Nguyen et al in Proceedings of ISCAS, 2006) and the HP version of Silva structure (Silva et al in Electron Lett 37(12):737---738, 2001) which has the additional advantages of reduced sensitivity to switch and op-amp nonlinearities and reduced op-amp voltage swings requirement as first stages of this new cascade technique The first-stage made up of Silva-based feedforward HP structure proves to be a better choice because of its insensitivity to op-amp non-idealities The method of designing cascade consists of approximating quantizer-gain by functional simulation of the modulator and then keeping this value in view while designing digital filters Digital filters designed this way are more efficient in cancelling quantization error and provide better results System level simulations have been performed in Matlab and transistor level simulations have been carried out in SPECTRE, both of which prove the efficacity of our approach
3 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...The SNR can still be increased by using more bits in the internal quantizer, but this requires a multi-bit ADC and also means to insure the in-band linearity of the internal DAC [7]....
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...However, the gain of a binary quantizer is not defined so easily because a binary quantizer has only one threshold [7]....
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TL;DR: In this paper, a noise-coupled time-based continuous-time sigma-delta modulator based on the asynchronous pulse width modulator (APWM) and the time-to-digital converter (TDC) is presented.
Abstract: Translation of the amplitude axis to the time axis can be a promising approach to alleviate the analog-to-digital converter's resolution problems in low-voltage CMOS circuits. From this point of view, a noise-coupled time-based continuous-time sigma-delta modulator (TCSDM) based on the asynchronous pulse width modulator (APWM) and the time-to-digital converter (TDC) is presented. Noise-coupling is realized by extracting the time quantization error of the TDC and injecting its delayed version to the input of the APWM. By using a novel implementation of the noise-coupling technique in the proposed TCSDM, the modulator's noise-shaping order is improved by one. Unlike the conventional noise-coupled sigma-delta modulators, in the proposed structure, the need of an extra subtractor at the quantizer input is resolved through merging the excess loop delay compensation path with the proposed noise-coupling branch. Comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed time-based modulator. To confirm the validity of the proposed structure, the effects of main circuit non-idealities in the modulator's performance are taken into consideration and the related simulation results are investigated. A digital-friendly implementation of the quantizer in the proposed modulator makes it suitable for low-voltage nanometer CMOS technologies.
3 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...The loop filter design is commonly performed in discrete-time domain by realizing the desired H(z) as NTF(z) = 1/(1 ? H(z)) via the delta-sigma toolbox [24]....
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...They are either at DC or complex-conjugate and cause the NTF frequency response to have a notch at the frequencies of the optimal zeros [24]....
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Patent•
13 Feb 2015TL;DR: In this paper, a delta-sigma modulator (10) comprises a modulator loop (11) and a code generator (12), which is configured to generate a generator signal (BS) that is realized as an extended Barker code.
Abstract: A delta-sigma modulator (10) comprises a modulator loop (11) and a code generator (12). The modulator loop (11) comprises a loop filter (18). The code generator (12) is configured to generate a generator signal (BS) that is realized as an extended Barker code. The code generator (12) comprises a generator output (23) that is coupled to the loop filter (18).
3 citations
References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations