Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
More filters
24 Jun 2012
TL;DR: Behavioural and transistor-level simulation results confirm that the proposed recording module for peripheral neural signals is capable of recording neural signals in the order of magnitude of tens of μΥ eliminating the huge low frequency noise due to electromyographic interferences.
Abstract: A recording module for peripheral neural signals is presented. The proposed device, based on a sigma-delta architecture, is made up of two main parts: an analog module as front-end stage for neural signal acquisition, pre-filtering and sigma-delta modulation and a digital unit for sigma delta decimation and system configuration. The analog module provides a gain of 200V/V in a 800Hz–8kHz frequency range, while the sigma-delta converter grants a 9bit resolution and a good noise rejection thanks to the 32 order decimator IIR filter. Behavioural and transistor-level simulation results confirm that the system is capable of recording neural signals in the order of magnitude of tens of μΥ eliminating the huge low frequency noise due to electromyographic interferences.
3 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...In order to remove the EMG noise at low frequencies and the quantization noise pushed at high frequencies by the analog modulator, it is necessary to use a high-order bandpass antialiasing filter as the first decimator stage, before the downsampler....
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TL;DR: In this article, the authors suggest a method for high level circuit analysis that is based on using common (open source or low cost) circuit simulators but precise and fast enough to meet requirements imposed by demanding mixed-signal blocks.
Abstract: Concerning the fact that the design of contemporary integrated circuits (IC)
is practically impossible without using sophisticated Electronic Design
Automation (EDA) software, this paper gives some interesting thoughts and
considerations about that issue. As technology processes advances on year
basis consequently EDA industry is forced to follow this trend as well. This,
on the other hand, requires IC designer to frequently and efficiently
accommodate to new working environments. Authors of this paper suggest a
method for high level circuit analysis that is based on using common (open
source or low cost) circuit simulators but precise and fast enough to meet
requirements imposed by demanding mixed-signal blocks. The paper demonstrates
the proposed EDA procedure on an example of second order ΔΣ modulator design.
It illustrates considerable simulation time saving which is more than welcome
in a world of analogue and mixed-signal design. [Projekat Ministarstva nauke
Republike Srbije, br. TR32004: Advanced technologies for measurement,
control, and communication on the electric grid]
3 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...The reader is advised to look in [6] for the details about spectral estimation....
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13 Oct 2011
TL;DR: A compact mathematical model for predicting and analyzing Delta-Sigma modulator's spurious tones and it outputs an accurate quantization noise estimate array for an arbitrary modulator stimulus: dc, ramp, sinusoid, two-tone, etc.
Abstract: This paper proposes a compact mathematical model for predicting and analyzing Delta-Sigma modulator's spurious tones. The model is based on frequency modulation and it outputs an accurate quantization noise estimate array for an arbitrary modulator stimulus: dc, ramp, sinusoid, two-tone, etc. For predicting the pattern noise or limit cycles, the proposed estimation model was found very precise. The model is applicable to a wide range of Delta-Sigma modulator types: low- and high-order, single- and multibit as well as to low- and band-pass types. The proposed model also takes different quantizer types (mid-rise and mid-tread) into account. The in-band quantization noise estimate can be used to predict the modulator's performance.
3 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...All simulations in this work were performed using DeltaSigma toolbox’s [12] ’simulateDSM’ function....
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...The amplitude of idle tones does not change with time, but the tone mechanism is a complicated function of stimulus [12]....
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Dissertation•
28 Jan 2019
TL;DR: In this article, the authors focus on Single-Event Effects (SEE) causats per the recol·leccio de carrega degut a l'impacte d'una particula ionitzant en un node d'un circuit microelectronic.
Abstract: Introduccio Aquesta tesi es centra en els anomenats Single-Event Effects (SEE) causats per la recol·leccio de carrega degut a l'impacte d'una particula energetica en un node d’un circuit microelectronic.
En les ultimes decades la tecnologia microelectronica ha experimentat un escalat constant permetent el disseny i implementacio de sistemes mes rapids, mes complexos i compactes.
Aquest escalat ve acompanyat per la disminucio de la tensio d'alimentacio i la reduccio de les mides dels transistors, fenomens que tenen per efecte col·lateral un augment en la probabilitat de que una particula ionitzant que interactua amb el substrat semiconductor puga generar la carrega suficient per induir efectes transitoris que afectin el correcte funcionament del circuit electronic i causar aquests SEEs. D'aquesta forma, els efectes de la radiacio ionitzant ja no son un problema especific exclusivament relacionat amb aplicacions espacials o avionica, convertint-se en una preocupacio important per a la fiabilitat dels dispositius electronics emergents.
Aquests SEEs es poden dividir en els anomenats Single-Event Upsets (SEU) si produeixen un canvi en l'estat logic d'un element de memoria i els anomenats Signle-Event Transients (SET) si es genera una variacio transitoria en el voltatge d’un o mes nusos en un circuit combinacional. Ambdos SEEs es produeixen degut a la generacio de parells electro-forat com a consequencia de les interaccions de particules amb la xarxa cristal·lina de silici que forma el susbstrat dels dispositius d’estat solid en els circuits integrats. Les particules alfa, neutrons, protons, ions pesats i altres particules ionitzants poden interactuar amb dispositius d'estat solid i afectar aixi el seu comportament. Aquest efecte sols es produeix quan la carrega recol·lectada sobrepassa un determinat valor llindar (carrega critica), la qual depen de la tecnologia de fabricacio, del disseny a nivell de circuit, disposicio dels components i de les caracteristiques transitories de la corrent induida.
- Contingut de la investigacio Aquesta tesi s'ha centrat en l'estudi dels SEUs en dos dissenys diferents de cel·les SRAM, ressaltant un estudi comparatiu entre les cel·les de mida minima de sis transistors (6T) i de vuit transistors (8T). D'aquesta manera, el treball aqui presentat mostra els resultats de l'exposicio de les SRAMs a diferents entorns operatius tals com una font alfa, una font de protons, una font de neutrons i un camp mixt d'alta energia, caracteritzat aquest ultim per contindre espectres de particules mes energetiques, (fins als GeV) i un conjunt mes ampli d'especies de particules (incloent pions carregats).
Tambe s'estudia l'estabilitat dels convertidors analogic-digitals (A/D) per SET, utilitzant un disseny de modulador ΣΔ per a calcular si per a nivells raonables de carrega induida, la inestabilitat pot ser activada per SET.
- Conclusio Amb l'objectiu de destacar alguns resultats interessants obtinguts en la tesi: • La presencia de MBU es mes evident quan la SRAM esta exposada a particules d'alta energia, un efecte que es mes pronunciat en les cel·les 6T.
• Els valors de la seccio transversal obtinguts a partir dels resultats experimentals de les cel·les 6T estan d'acord amb els valors publicats anteriorment. Els resultats mostren que independentment del nombre de transistors que componen les cel·les de memoria, el nombre total d'esdeveniments registrats es bastant similar quant a que els dispositius tenen la mateixa mida. No obstant aixo, el percentatge de MBU es clarament mes alt en 6T que en 8T donada la major densitat inherent de 6T a mes de l'aillament proporcionat pel circuit de lectura en 8T.
• Un altre resultat interessant es que les SRAM van revelar la vulnerabilitat als neutrons durant les proves realitzades en el Centre Nacional d'Acceleradors (CNA).
• S'ha demostrat que un SET pot activar la inestabilitat en els moduladors ΣΔ. En aquest cas, el rendiment del convertidor A / D es redueix en gran mesura, pero no es detecta de forma senzilla a partir del flux de bits de sortida. Aixo implica que un SET podria conduir a adquisicions incorrectes a llarg termini.
3 citations
TL;DR: The presented proof-of-concept design makes use of time interleaving two third-order I-
Abstract: High-resolution, single-loop incremental Delta-Sigma (I- $\Delta \Sigma $ ) ADCs require large oversampling ratios to sufficiently suppress quantization noise. This limits the bandwidth of most designs to the low-kHz range. To overcome this problem, the presented proof-of-concept design makes use of time interleaving two third-order I- $\Delta \Sigma $ modulators with embedded hardware sharing that helps to enhance the efficiency of the presented modulator. The modulator is fully reconfigurable in a way that both channels can either be operated time interleaved or independent from each other. This is a means of enhancing the flexibility and efficiency of the modulator depending on the application scenario. The presented design was fabricated in a 180nm technology node.
3 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...merit (FoMs), can now be implemented in a more efficient way [8]....
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References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations