Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
More filters
01 Dec 2013
TL;DR: A digital-to-RF converter (DRFC) architecture for IQ modulator that utilizes a low pass ΣΔ modulator and a semi-digital FIR filter and simulation results are presented to support the feasibility of the solution.
Abstract: A digital-to-RF converter (DRFC) architecture for IQ modulator is proposed in this paper. The digital-RF converter utilizes the mixer DAC concept but a discrete-time oscillatory signal is applied to the digital-RF converter instead of a conventional continuous-time LO. The architecture utilizes a low pass ΣΔ modulator and a semi-digital FIR filter. The digital ΣΔ modulator provides a single-bit data stream to a current-mode SDFIR filter in each branch of the IQ modulator. The filter taps are realized as weighted one-bit DACs and the filter response attenuates the out-of-band shaped quantization noise generated by the ΣΔ modulator. To find the semi-digital FIR filter response, an optimization problem is formulated. The magnitude metrics in out-of-band is set as optimization constraint and the total number of unit elements required for the DAC/mixer is set as the objective function. The proposed architecture and the design technique is described in system level and simulation results are presented to support the feasibility of the solution.
3 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...Utilizing a digital Σ∆ modulator in an oversampling D/A converter potentially enables us to achieve the same in-band performance compared to a Nyquist-rate DACs but with fewer DAC unit elements and hence we gain in terms of clocking, signal routing and unit element matching [11]....
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01 Dec 2011
TL;DR: In this article, a photonic analog-to-digital converter (ADC) based on asynchronous delta-sigma modulation technique (ADSM) has been investigated and demonstrated.
Abstract: A novel photonic analog-to-digital converter (ADC) based on asynchronous delta-sigma modulation technique (ADSM) has been investigated and demonstrated The ADSM architecture utilizes photonic leaky integrators, inverted bistable quantizer and positive corrective feedback suitable for non-interferometric optical implementation The principles of the proposed 2nd -order ADSM are modeled and simulated mathematically A prototype fiber-optic ADSM is constructed, producing acceptable NRZ type binary output for frequencies in the MHz range For an input of 2 MHz and sampling rate of 108 MHz, the prototype achieves SNR of 398 dB, SFDR of 212 dB and ENOB of 6 in the 54 MHz bandwidth of interest
3 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...INTRODUCTION Achieving high speed, high resolution analog-to-digital (A/D) conversion is a difficult technological problem [1]....
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TL;DR: In this paper, a multi-stage noise-shaping (MASH) sigma-delta (ΣΔ) modulator is proposed to be used in low oversampling ratio (OSR) applications and utilizes a noise-shaped two-step analog-to-digital converter (ADC) in the second stage to provide an extra attenuation of the quantization noise.
3 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...In low OSRs, the SQNR improvement due to the additional order will be less effective [1]....
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...Sigma-delta modulators are known as their high accuracy is achieved by noise-shaping together with oversampling [1]....
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Dissertation•
22 Nov 2010
TL;DR: Results show that the proposed design ideas are useful for low-power and wideband delta-sigma modulators which have low OSR, and various double-sampling scheme s are studied, and novel schemes are presented to achieve wideband operation without noise folding effect.
Abstract: approved:_________________________________ _______________ Gabor C. Temes As CMOS processes keep scaling down devices, the ma ximum operating frequencies of CMOS devices increase, and hence cir uits can process very wide band signals. Moreover, the small physical dimensio ns f transistors allow the placing of many more blocks into a single chip, inc luding highly accurate analog blocks and complicated digital blocks, which can pr ocess audio to communication data. Nowadays, wideband and low-power data convert er is mandatory for mobile applications which need a bridge between analog and digital blocks. In this dissertation, low-power and wideband techni ques are proposed. An embedded-adder quantizer with dynamic preamplifier is proposed to achieve powerefficient operation. Various double-sampling scheme s are studied, and novel schemes are presented to achieve wideband operation without noise folding effect. To reduce timing delay and idle tones, a high speed DEM which alternates two sets of comparator references is proposed. Multi-cell ar chitecture is studied to insure higher performance when the number of modulators in creases. 0.18 μm double-poly/4-metal CMOS process was used to impl e ent a prototype IC. 20 MHz signal bandwidth was achieved with a 320 MHz sampling clock. The peak SNDR was 63 dB. The figure-of-merit FoM = P/(2 *BW*2 ) was 0.35 pJ/conversion, with a 16 mW power consumption. Meas urement results show that the proposed design ideas are useful for low-power and wideband delta-sigma modulators which have low OSR. A second-order noise-coupled modulator with an embe dded-zero optimization was proposed to reduce power consumption by elimina ting some of the integrators. This architecture makes easier the implementation o f the small feedback capacitors for high OSR modulators.
3 citations
01 Oct 2018
TL;DR: An intelligent packet transmission system between an Ethernet and a synchronous optical network involving format transformation based on a field-programmable gate array (FPGA) development board and implemented using the Verilog hardware description language.
Abstract: This paper presents an intelligent packet transmission system between an Ethernet and a synchronous optical network involving format transformation based on a field-programmable gate array (FPGA) development board. Client data are fed to the RS485 port on the FPGA board (Tx) and then transformed into an Ethernet packet. The E/O converter (Tx) converts an electrical signal to an optical signal and transmits it through the optical fiber to the receiver. The O/E converter (Rx) converts an optical signal to an electrical signal, which is captured using the FPGA board. The signal is then sent to the client through the RS485 port. The client terminal can display the received data to verify the transceiver function. Optical fiber transmission has properties such as high speed, long distance, and low interference, whereas electrical transmission does not possess these features. The intelligent packet transformation and transmission mechanisms were implemented using the Verilog hardware description language and verified through the FPGA development board on the RS485 serial port. The measured results indicated that the operational frequency, data transfer rate of the RS485 port, power consumption, and chip size were 125 MHz, 115,200 bps, 137 mW, and 1.27 × 1.27 mm^2, respectively, at a data volume of 8 bits and a first-in-first-out queue of 1K bytes.
3 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...Moreover, Ethernet is a popular LAN protocol [4]....
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References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations