Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
More filters
25 Sep 2014
TL;DR: A high-speed low-power decimation filter with programmable decimation ratios (32, 64 and 128) and sampling rates (624MHz, 312MHz and 208MHz) for LTE application and a Signal-to-Noise Ratio of 69dB over the signal bandwidth is presented.
Abstract: This paper discusses the design of high-speed low-power decimation filter for wideband Delta-Sigma ADC. It presents a low power decimation filter with programmable decimation ratios (32, 64 and 128) and sampling rates (624MHz, 312MHz and 208MHz) for LTE application. The decimation filter has five different operating modes and consists of three sinc filters, two halfband filters and a FIR filter. It uses power efficient polyphase decomposition filter with a wise clock distribution approach to minimize power consumption. The decimation filter is implemented in 130 nm CMOS process, which consumes 0.46 × 0.46 mm2 cell area. Simulation results show that when Sigma-Delta modulator output sampling frequency is 624MHz, 312MHz and 208MHz, it consumes less than 4.6mW, 2.3mW and 1.5mW from 1.2V supply respectively. In addition, they all achieve a Signal-to-Noise Ratio of 69dB over the signal bandwidth.
3 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...INTRODUCTION Delta-Sigma Analog to Digital Converter (ADC) is widely used in wireless communication systems due to low power consumption, higher resolution and small silicon area [1]....
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26 Mar 2018
3 citations
28 Dec 2015
TL;DR: Based on high-level VerilogA simulations, the performance of the ΔΣ modulator versus various block performance parameters is presented as trade-off curves and based on these results, the block specifications are derived.
Abstract: In this paper the system level design of a continuous-time ΔΣ modulator for portable ultrasound scanners is presented. The overall required signal-to-noise ratio (SNR) is derived to be 42 dB and the sampling frequency used is 320MHz for an oversampling ratio of 16. In order to match these requirements, a fourth order, 1-bit modulator with optimal zero placing is used. An analysis shows that the thermal noise from the resistors and operational transconductance amplifier is not a limiting factor due to the low required SNR, leading to an inherently very low-power implementation. Furthermore, based on high-level VerilogA simulations, the performance of the ΔΣ modulator versus various block performance parameters is presented as trade-off curves. Based on these results, the block specifications are derived.
3 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...A continuoustime delta-sigma modulator is selected over a discrete-time due to its lower power and higher frequency operation range [3], [4]....
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27 May 2018
TL;DR: It is demonstrated that MSLA SDMs are a viable alternative to conventional single-bit SDMs when better performance with moderate additional hardware complexity are required.
Abstract: A hardware architecture for the implementation of Multi-Step Look-Ahead Sigma-Delta Modulators (MSLA SDMs) is presented. MSLA SDMs offer superior performance than conventional single-bit SDMs for a multitude of applications relying on single-bit signal representation. However, traditional look-ahead SDMs have very high algorithmic complexity and their hardware implementation does not allow for real-time operation. MSLA SDMs overcome this problem by transforming the minimization problem associated with traditional look-ahead SDMs. A proof-of-concept FPGA implementation of a specific MSLA SDM is discussed and compared to a conventional single-bit SDM in terms of performance and hardware complexity. It is demonstrated that MSLA SDMs are a viable alternative to conventional single-bit SDMs when better performance with moderate additional hardware complexity are required.
3 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...Sigma-Delta modulators (SDMs) are used to convert an analog or digital multi-bit signal to a few-bit or single-bit one by exploiting oversampling to shape the quantization noise outside the signal frequency band [1]....
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...An SDM with a single-bit quantizer is less stable than one with a multi-bit quantizer [1]....
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16 Aug 2010
TL;DR: A new low-power switched-capacitor integrator is proposed for high-resolution ΔΣ ADCs that achieves much lower power dissipation for the same noise specifications.
Abstract: A new low-power switched-capacitor integrator is proposed for high-resolution ΔΣ ADCs. Compared to the conventional switched-capacitor integrator, it achieves much lower power dissipation for the same noise specifications. To verify the effectiveness of the new integrator, and to compare it with the conventional one, a third-order delta-sigma modulator was simulated. A detailed comparison between the conventional SC integrator and the proposed SC integrator is also presented.
3 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...The power of the sampling noise voltage during Φ1 is kT/(OSR·Cs) [2]....
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References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations