Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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01 Jan 2006
TL;DR: In this article, the authors describe architectures for bandpass and quadrature bandpass ADCs and examine several circuit considerations associated with operation at sampling rates in the 100-MHz range.
Abstract: A bandpass ADC digitizes a bandpass signal directly, without prior conversion to baseband. Bandpass ADCs are well-suited to wired and wireless receivers, and can reduce system complexity, increase integration and improve performance. This paper describes architectures for bandpass and quadrature bandpass ADCs and examines several circuit considerations associated with operation at sampling rates in the 100-MHz range.
3 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...1 As described in the literature [1-5], the key to achieving this reduced sampling rate is to concentrate the zeros of the ∆Σ modulator’s noise transfer function (NTF) in the band of interest, specifically in the vicinity of 10....
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...5 of [5]....
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11 May 2015
TL;DR: This paper presents the design and evaluation of a ΣΔ-modulator based analog-to-digital converter (ADC) for direct RF digitization within a multi-standard vehicular connectivity architecture.
Abstract: This paper presents the design and evaluation of a ΣΔ-modulator based analog-to-digital converter (ADC) for direct RF digitization within a multi-standard vehicular connectivity architecture. Upcoming trends and changes which will require new architecture concepts for connectivity in the automotive domain are discussed. Hardware requirements are derived. Based on these goals, a reconfigurable ADC is designed with capabilities of digitizing all relevant wireless services for vehicular use within the frequency range of 600 MHz to 6 GHz. A performance assessment is done based on evaluation of the signal to noise ratio within a realistic use case where multiple services at different frequencies are successfully digitized.
3 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...The feedback of the output signal ysd(n) is done by a DAC with a finite impulse response (FIR-DAC)....
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...It consists of a broadband antenna which covers the specified spectrum as well as an analog-todigital converter (ADC) in the receiving path and a digitalto-analog converter (DAC) in the transmitting path....
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...The overall transfer function in the s-domain including the excess-loop-delay-elements fE and z−1 is H(s,v) = 2∑ m=1 HFIR−DAC,m(s) + fEe−s (7) where the normalized sampling frequency v = fs/(2fn)....
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...Thus, depending on the choice of the FIR-DAC and the coefficents from Fig....
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...Here we utilize a not-return-to-zero DAC [9] with HDAC(s) = 1 for t ∈ [0;Ts/2] and HDAC(s) = 0 else....
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Proceedings Article•
01 Mar 2010Abstract: A low power high performance Delta-Sigma modulator for portable measurement applications is presented in this paper. To reduce the power consumption and ensure high performance, a comprehensive system-level design adopting a new method to determine the DC gain value of Operational Transconductance Amplifier (OTA) and considering the effect of 1/f noise is introduced. Besides, a novel power efficient current mirror Class-AB OTA with a fast-settling less-error switched-capacitor common-mode feedback (SC CMFB) circuit is proposed in this design. And the bottom terminal parasitic-effect of Poly-Insulator-Poly (PIP) capacitors is also considered. Therefore, about extra 20% of the capacitance is added to the total capacitance load. In addition, an area-efficient power-efficient resonator is adopted to realize a coefficient of 1/90 for 50% power and 75% area cost reduction over the conventional design. The chip is implemented in a low cost standard 0.35μm CMOS. Its total power is only 20μW at a 1.5V supply, and the measured Dynamic Range (DR) is 95dB over the 1 kHz bandwidth. The designed modulator shows very high Figure-of-Merit (FOM) among the recent low power high performance modulators. Keywords–low power, high performance, Delta-Sigma modulator, switched capacitor circuits
3 citations
24 Mar 2014
TL;DR: This paper proposes to reconfigure the internal Multiplying DACs (MDACs) that perform residue amplifications as integrators, each one with an analog and a digital input, to reuse consecutive pipeline stages to form ΣΔ modulators, with very reduced area overhead.
Abstract: Pipeline Analog to Digital Converters (ADCs) are widely used in applications that require medium to high resolution at high acquisition speed. Despite of their quite simple working principles, they usually form rather complex mixed-signal blocks, particularly if digital correction and calibration are considered. As a result, pipeline converters are difficult to test and diagnose. In this paper, we propose to reconfigure the internal Multiplying DACs (MDACs) that perform residue amplifications as integrators, each one with an analog and a digital input. In this way, we can reuse consecutive pipeline stages to form ΣΔ modulators, with very reduced area overhead. We thus get an on-chip DC (low-frequency) probe with a digital 1-bit output that does not require any extra pin. In addition, digital test techniques developed for ΣΔ modulators may be used to enhance the diagnosing capabilities. An industrial 1.8V 15-bit 100Msps pipeline ADC that had previously been fully validated in a 0.18μm CMOS process is used as a case of study for the introduction of the DfT modifications.
3 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...…the idea consists in measuring the errors in the MDACs (including gain errors), using the own back-end ADC (constituted by the least significant stages to the specific one under calibration) as measurement instrument, and updating accordingly the associated stage sub-code in a Look-Up Table (LUT)....
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TL;DR: In this paper, the anti-aliasing characteristic is locked into a shape that maximally prevents aliasing to low frequencies, and a bilinear integrator is introduced for eliminating the impact of the ripple reduction loop on the system's DC gain.
Abstract: We present a compact, versatile Hall readout system with digital output, fully integrated in 180nm technology. The core of the system is an instrumentation amplifier architecture that provides inherent anti-aliasing filtering, where the anti-aliasing characteristic is locked into a shape that maximally prevents aliasing to low frequencies. The efficiency for blocking out-of-band white noise is comparable to that of a second-order filter, eliminating the need for an explicit anti-aliasing filter before the ADC. Chopping/spinning is applied for up-modulating offset and 1/f noise to just beyond the signal band. A mostly-digital ripple reduction loop (RRL) is added for mitigating offset-related dynamic range limitations. In this, a bilinear integrator is introduced for eliminating the impact of the RRL on the system’s DC gain. Moreover, the resolution of the DAC generating the analog offset compensation is reduced significantly, and the effect thereof is eliminated by digital noise cancellation logic. The one-step amplification and the simple, low-resolution DAC for offset compensation both aid in keeping the area footprint low: the analog circuits (including DAC and ADC) only occupy 0.21mm2. Notable performance characteristics are an input-referred noise floor of 55nT/ $\sqrt {{\mathrm {Hz}}}$ within a 410kHz bandwidth, a current consumption of only 5.1mA, and a 47dB dynamic range. The amplifier architecture can be easily applied as an analog preconditioning circuit in other sensor readout situations as well.
3 citations
References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations