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Understanding Delta-Sigma Data Converters
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TLDR
This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.Abstract:
Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.read more
Citations
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Journal ArticleDOI
Less jitter sensitive NTF design for NRZ multi-bit continuous-time Delta-Sigma modulators
TL;DR: This paper studies the clock jitter error in multi-bit continuous-time Delta-Sigma modulators with non-return-to-zero (NRZ) feedback waveform and proposes a few useful formulas for the design of a less jitter sensitive NTF.
Journal ArticleDOI
Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC
TL;DR: A direct digital-to-RF converter (DRFC) is presented in this work, which benefits from technology scaling and can be monolithically integrated into advance dSPs.
Proceedings ArticleDOI
An area-efficient digitally-assisted DC canceling loop for high sensitivity UHF RFID receiver
TL;DR: An area-efficient digitally-assisted DC canceling loop is presented for high sensitivity single-chip UHF RFID readers that suppresses the DC blocker in RFID receivers by 41 dB with the aid of negative feedback.
Journal ArticleDOI
A fourth-order bandwidth-reconfigurable delta—sigma modulator for audio applications
TL;DR: In this article, a single loop fourth-order delta-sigma modulator is presented for audio applications, which achieves an 89.3 dB SNR and 90.2 dB dynamic range in 16 kHz mode, as well as a 90.5 dB and 86 dB in 8 kHz mode.
Event-Based Compression Circuits for Neural Recording
TL;DR: This research shows that the IF encoder in current-mode implementation for data conversion is a promising alternative to conventional voltage-based and synchronous analog-to-digital converter (ADC) based approaches.
References
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Journal ArticleDOI
A higher order topology for interpolative modulators for oversampling A/D converters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Journal ArticleDOI
Decimation for Sigma Delta Modulation
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Journal ArticleDOI
An analysis of nonlinear behavior in delta - sigma modulators
Sasan H. Ardalan,J.J. Paulos +1 more
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Book ChapterDOI
The Structure of Quantization Noise from Sigma-Delta Modulation
James C. Candy,O. Benjamin +1 more
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Journal ArticleDOI
A fourth-order bandpass sigma-delta modulator
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.