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Understanding Delta-Sigma Data Converters

TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
More filters
Journal ArticleDOI
TL;DR: A new type of poly-phase decomposition is presented that keeps the critical path for each number of channels constant and minimizes the number of full-adders in the TI delta-sigma modulator (DSM).

2 citations

Journal ArticleDOI

2 citations


Cites methods from "Understanding Delta-Sigma Data Conv..."

  • ...On the other hand, since the ΔΣAD modulator reduces the quantization noise in the desired signal band by oversampling and noise-shaping technique, it is suitable to realize the high SNDR ADC in nanometer CMOS technology [3]....

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Proceedings ArticleDOI
01 Dec 2010
TL;DR: An optimization method for designing area-constrained SAR ADC with highest possible energy efficiency for a given dynamic range (DR) is proposed, able to minimize power dissipations by reducing the size of the unit capacitor area without dynamic range degradation due to capacitor mismatch.
Abstract: In this paper, the trade-off between device mismatch, quantization noise and device noise in successive approximation register analog to digital converter (SAR ADC) is investigated. An optimization method for designing area-constrained SAR ADC with highest possible energy efficiency for a given dynamic range (DR) is proposed. By taking device noise and process mismatch information into account, it is able to minimize power dissipations by reducing the size of the unit capacitor area without dynamic range degradation due to capacitor mismatch. As a case study, a low power 12 bits SAR ADC has been designed in 0.18um CMOS process, with 1–100 kHz sample rate.

2 citations

01 Jan 2012
TL;DR: In this paper, a novel structure for direct charge transfer pseudo-n-path (DCT-PNP) resonator based on FDCCII was presented, which not only had the advantages of the conventional opamp based DCT, but also the capability of switching at high frequencies due to the inherent characteristics of CCII.
Abstract: In this paper a novel structure for ‘Direct Charge Transfer Pseudo-N-Path’ (DCT-PNP) resonator based on ‘Fully Differential Second Generation Current Conveyor’ (FDCCII), is presented. This structure not only had the advantages of the conventional opamp based DCT-PNP, but also the capability of switching at high frequencies due to the inherent characteristics of CCII. Furthermore, the number of the switches was reduced to 21 compared with the traditional DCT-PNP resonator which had 24 switches. The proposed resonator was simulated by means of HSPICE and WAVEVIEW in 0.35µm CMOS technology.

2 citations


Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...For more discussion regarding the switching noise one can refer to [20]....

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Patent
05 Feb 2015
TL;DR: In this paper, a switching component comprises a plurality of switches configured to receive a differential signal at an input and is configured to provide a non-inverted version of the differential signals at an output during a first phase of operation and an inverted version of signals at a second phase of operations.
Abstract: A switching component comprises a plurality of switches configured to receive a differential signal at an input and is configured to provide a non-inverted version of the differential signal at an output during a first phase of operation and an inverted version of the differential signal at an output during a second phase of operation. A driver amplifier component is configured to receive the non-inverted version of the differential signal at an input during the first phase of operation and the inverted version of the differential signal at an input during the second phase of operation. A sampling capacitor component is configured to sample the output of the driver amplifier component during the first phase of operation and the second phase of operation.

2 citations

References
More filters
Journal ArticleDOI
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

399 citations

Journal ArticleDOI
James C. Candy1
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.

342 citations

Journal ArticleDOI
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

284 citations

Book ChapterDOI
James C. Candy1, O. Benjamin1
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.

255 citations

Journal ArticleDOI
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >

211 citations