Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
More filters
TL;DR: A filterless method that can remove the external LC filter is employed, which offers great advantages in terms of PCB space and system cost.
Abstract: A low-distortion third-order class-D amplifier that is fully integrated into a 0.18-μ m CMOS process was designed for direct battery hookup in a mobile application. A class-D amplifier for direct battery hookup must have a sufficiently high power supply rejection ratio (PSRR) in preparation for noise, such as when a global system for mobile communications (GSM) bursts ripples through the system power line. This amplifier has a high PSRR of 88 dB for 217-Hz power supply ripples, using a third-order loop filter. System performance and stability are improved by applying the design technique of input-feedforward delta-sigma (ΔΣ) modulators to the pulse-width modulation (PWM) class-D amplifier. A filterless method that can remove the external LC filter is employed, which offers great advantages in terms of PCB space and system cost. This amplifier achieves a power efficiency of 85.5% while delivering an output power of 750 mW into an 8-Ω load from a 3.7-V supply voltage. Maximum achieved output power at 1% total harmonic distortion plus noise (THD+N) from a 4.9-V supply voltage into an 8-Ω load is 1.15 W. This class-D amplifier is designed to have a broad operational range of 2.7-4.9 V for the direct use of mobile phone battery power. It has a total area of 1.01 mm2 and achieves a THD+N of 0.018%.
43 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...As shown in (4), the higher the quantizer level, the less the stability concern....
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...TABLE I SIMULATION RESULTS OF OP-AMPS The noise performance of the first op-amp is one of the most important design considerations [7]....
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...In general, third- or higher-order 1-bit modulators can become unstable easily if the input level is high [7], [8]....
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...This can be implemented by connecting the input signal to a point right in front of the comparator, as shown in Fig....
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TL;DR: This paper presents the first published fully-integrated digital fractional- N PLL based on a second-order frequency- to-digital converter (FDC) instead of a time-to- digital converter (TDC).
Abstract: This paper presents the first published fully-integrated digital fractional- $N$ PLL based on a second-order frequency-to-digital converter (FDC) instead of a time-to-digital converter (TDC). The PLL's quantization noise is nearly identical to that of a conventional analog delta-sigma modulator based PLL ( $\Delta\Sigma$ -PLL). Hence, the quantization noise is highpass shaped and is suppressed by the PLL's loop filter to the point where it is not a dominant contributor to the PLL's output phase noise. However, in contrast to a $\Delta\Sigma$ -PLL, the new PLL has an entirely digital loop filter and its analog components are relatively insensitive to non-ideal analog circuit behavior. Therefore, it offers the performance benefits of a $\Delta\Sigma$ -PLL and the area and scalability benefits of a TDC-based digital PLL. Additionally, the PLL's digitally controlled oscillator (DCO) incorporates a new switched-capacitor frequency control element that is insensitive to supply noise and parasitic coupling. The PLL is implemented in 65 nm CMOS technology, has an active area of 0.56 mm $^{2}$ , dissipates 21 mW from 1.0 and 1.2 V supplies, and its measured phase noise at 3.5 GHz is $-$ 123, $-$ 135, and $-$ 150 dBc/Hz at offsets of 1, 3, and 20 MHz, respectively. The PLL's power consumption is lower than previously published digital PLLs with comparable phase noise performance.
43 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...Unfortunately, even in the absence of non-ideal circuit behavior, first-order modulators are notorious for having quantization noise that varies widely with input amplitude and contains strong spurious tones [51]....
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...The resampled version of is applied to an oversampled error-feedback second-order digital modulator with LSB dither [51]....
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..., see [51], imply that the ADC output sequence can be written as...
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TL;DR: A wideband phase-locked loop (PLL)-based G/FSK transmitter (TX) architecture with a proposed sigma-delta modulated phase rotator (¿¿-PR) that adopts the input signal as the phase transition trigger, facilitating a glitch-free operation.
Abstract: A wideband phase-locked loop (PLL)-based G/FSK transmitter (TX) architecture is presented in this paper In the proposed TX, the G/FSK data is applied outside the loop; hence, the data rate is not constrained by the PLL bandwidth In addition, the PLL remains locked all the time, preventing the carrier frequency from drifting In this architecture, the G/FSK modulation signal is generated from a proposed sigma-delta modulated phase rotator (??-PR) By properly combining the multi-phase signals from the PLL output, the ??-PR effectively operates as a fractional frequency divider, which can synthesize modulation signals with fine-resolution frequencies The proposed ??-PR adopts the input signal as the phase transition trigger, facilitating a glitch-free operation The impact of the ??-PR on the TX output noise is also analyzed in this paper The proposed TX with the ??-PR is digitally programmable and can generate various G/FSK signals for different applications Fabricated in a 018 ?m CMOS technology, the proposed TX draws 63 mA from a 14 V supply, and delivers an output power of -11 dBm With a maximum data rate of 6 Mb/s, the TX achieves an energy efficiency of 15 nJ/bit
43 citations
TL;DR: This paper shows a first example of a concurrent readout system with single-ion channel resolution, using a compact and scalable architecture, and shows how formation of multiple artificial bilayer lipid membranes is automatically monitored by the interface.
Abstract: The convergence of integrated electronic devices with nanotechnology structures on heterogeneous systems presents promising opportunities for the development of new classes of rapid, sensitive, and reliable sensors. The main advantage of embedding microelectronic readout structures with sensing elements is twofold. On the one hand, the SNR is increased as a result of scaling. On the other, readout miniaturization allows organization of sensors into arrays. The latter point will improve sensing accuracy by using statistical methods. However, accurate interface design is required to establish efficient communication between ionic-based and electronic-based signals. This paper shows a first example of a concurrent readout system with single-ion channel resolution, using a compact and scalable architecture. An array of biological nanosensors is organized on different layers stacked together in a mixed structure: fluidics, printed circuit board, and microelectronic readout. More specifically, an array of microholes machined into a polyoxymethylene homopolymer (POMH or Delrin) device coupled with ultralow noise sigma-delta converters current amplifiers, is used to form bilayer membranes within which ion channels are embedded. It is shown how formation of multiple artificial bilayer lipid membranes (BLMs) is automatically monitored by the interface. The system is used to detect current signals in the pA range, from noncovalent binding between single, BLM-embedded ?-hemolysin pores and s-cyclodextrin molecules. The current signals are concurrently processed by the readout structure.
43 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...analog-to-digital converter (ADC) that samples the input signal at a frequency much greater than required by Shannon’s theorem and converts the information into a 1-bit stream [28]....
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...1-bit stream needs to be down-converted into digital words by means of a digital filter called a decimator [28]....
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18 Jun 2008
TL;DR: In this paper, a dual-mode SDA ADC for GSM/WCDMA applications with DR of 86 dB/63 dB for 100 KHz/1.92 MHz in a 65 nm CMOS technology with power consumption of 2.1 mW/3.2 mW.
Abstract: A technique to compensate for the harmful excess loop delay in a continuous time SigmaDelta analog-digital converter is presented. With no extra power consumption or area penalty the technique is suitable for variety of applications employing continuous time SigmaDelta analog-digital converters. This work presents a dual mode SigmaDelta ADC for GSM/WCDMA applications with DR of 86 dB/63 dB for 100 KHz/1.92 MHz in a 65 nm CMOS technology with power consumption of 2.1 mW/3.2 mW.
43 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...1-a) could be used to compensate for the extra delay in the loop while creating a desired Noise Transfer Function (NTF) [2], [3]....
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...A desirable NTF in z-domain could be mapped into the architecture of Fig.1-b by matching the impulse response of the discrete time loop filter to the continuous time model....
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...The technique of [2] for implementation of the direct feedback path has speed issues as the quantizer is driven by a high impedance source....
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...In this design a second order differentiation NTF: 2)11( −− z is chosen for noise shaping and a delay of T/2 (T is the sampling clock period) is allocated for the loop....
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...A direct feedback path (Fig.1-a) could be used to compensate for the extra delay in the loop while creating a desired Noise Transfer Function (NTF) [2], [3]....
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References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations