Open AccessBook
Understanding Delta-Sigma Data Converters
Reads0
Chats0
TLDR
This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.Abstract:
Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.read more
Citations
More filters
Proceedings ArticleDOI
Time-Interleaved Polyphase Decimation Filter Using Signed-Digit Adders
TL;DR: Time-interleaved technique is introduced to a polyphase FIR filter to overcome operation speed limitation due to the setup and hold time constraint for delayed flip-flops and it is found that in this architecture, the adder tree based on ternary signed-digit full adders effectively improves the operation speed.
On the realization of switched-capacitor integrators for sigma-delta modulators
TL;DR: This thesis will assume that an SFG description of the CRFB sigma-delta modulator has been designed and presents a structured method to obtain a circuit realization of the integrators in a specific modulator.
Journal ArticleDOI
A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT-$$\Updelta\Upsigma$$ΔΣ ADC with 1.5 cycle quantizer delay and improved STF
TL;DR: In this article, a 1 GS/s continuous-time delta-sigma modulator (CT- $$\Updelta\Upsigma$$ Δ Σ M) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB peak-SNDR is reported in a 0.13 μm CMOS technology.
Book ChapterDOI
System Aspects of Conversion
TL;DR: This chapter discusses a number of points related to the system interaction aspects of signal processing strategy play an important role for the application of an analog-to-digital converter.
Proceedings ArticleDOI
Two effective single-loop high-performance sigma-delta modulators based on 0.13µm CMOS
TL;DR: Two high-resolution medium-bandwidth single-loop 4th-order single-bit sigma-delta modulators using a feed-forward and a feedback topology respectively are implemented in 0.13µm CMOS technology and feedback structure gives better performance than feed- forward one.
References
More filters
Journal ArticleDOI
A higher order topology for interpolative modulators for oversampling A/D converters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Journal ArticleDOI
Decimation for Sigma Delta Modulation
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Journal ArticleDOI
An analysis of nonlinear behavior in delta - sigma modulators
Sasan H. Ardalan,J.J. Paulos +1 more
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Book ChapterDOI
The Structure of Quantization Noise from Sigma-Delta Modulation
James C. Candy,O. Benjamin +1 more
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Journal ArticleDOI
A fourth-order bandpass sigma-delta modulator
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.