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Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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25 May 2021
TL;DR: In this paper, an open-loop observer is used to compensate for the effects of digital-to-analog converters (DACs) errors, such as quantization error, nonlinearity, thermal and semiconductor noise, and glitches.
Abstract: The resolution of precision mechatronic systems is fundamentally limited by the noise and distortion performance of digital-to-analogue converters (DACs). The sources of noise and distortion include quantisation error, non-linearity, thermal and semiconductor noise, and glitches. In precision systems it is desirable to approach the theoretical performance limit in order to maximise dynamic range and bandwidth. Currently, effective methods exist to mitigate DAC error sources, except for glitches, which is the focus of this paper. A glitch compensation technique is introduced based on an open-loop observer that utilises knowledge about glitches while quantisation error mitigation remains intact. The compensation technique attempts to minimise the glitch effects present on the analogue output via additional control effort, combined with ΔΣ-modulation which is a method for mitigating quantisation error. The method is applied to a DAC model including the glitch effects and show significant improvements over earlier efforts.
2 citations
TL;DR: A sigma-delta third order dual truncation MASH 2-1 D/A converter with 18-bit input format is successfully implemented in 90nm CMOS technology and its measured harmonics are all below -100dB.
Abstract: A sigma-delta third order dual truncation MASH 2-1 D/A converter with 18-bit input format is successfully implemented in 90nm CMOS technology. This design focuses on the digital implementation of 64x upsampling digital interpolator and third-order delta-sigma MASH architecture. The interpolator is digitally designed by two cascading halfband FIR lowpass filter and the final stage is designed using CIC (Cascaded Integrator-Comb) filter. The third-order delta-sigma MASH modulator is implemented into two parts; these are digital part and analog part. The digital part is successfully implemented using RTL code while the analog part is thru MATLAB for behavioral and Cdesigner for actual implementation. The total area for the digital block is 30339.259853 μm while the total cell area is 25918.75 μm using the TSMC 0.13μm Logic CMOS Technology. Furthermore, the total dynamic power of the circuit (modulator and interpolator) while in operation is 11.1799 μW. With the 3-order dual truncation multistage noise shaping technology, SFDR of 110dB and SNR of 115 dB is achieved and its measured harmonics are all below -100dB. The total harmonic distortion of the whole analog block which has a chip area of 681um by 365um is 173m% and with a total power dissipation of 688.279uW.
2 citations
TL;DR: In this article, a three-level D-to-A sigma-delta converter for low consumption applications is presented, which can drive a loudspeaker directly without requiring passive components and with a sufficient audio quality.
Abstract: A new three-level D-to-A sigma–delta converter for low consumption applications is presented. The two one-bit outputs of this converter can drive a loudspeaker directly without requiring passive components and with a sufficient audio quality. The global consumption is minimised by reducing the number of active states.
2 citations
12 May 2019
TL;DR: In this article, the authors proposed a new ratio-metric interface for amplitude-modulated MEMS sensors based on mutually injection-locked oscillators (MILO), which is adapted for a sampling frequency up to 1MHz.
Abstract: In this paper, we propose a new ratio-metric interface for amplitude-modulated MEMS sensors based on mutually injection-locked oscillators (MILO). The two outputs are down-converted by a peak demodulator to improve the immunity to phase variation and noise. The peak values are then fed into a second-order discrete-time delta-sigma modulator that directly produces a digital ratio-metric output with a worst-case resolution greater than 16 bits and with input full scale of 0.6. The interface is clocked by the resonators output signal and is adapted for a sampling frequency up to 1MHz.
2 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...On the other hand, meeting the requirement of greater than 16 bits resolution with a 256 wc N OSR and a 1-bit quantizer, calls for a second or higher order modulator [9]....
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...This limits the use of CT-∆Σ in such applications where the master clock is generated by the resonators, and may vary from one sensor to another; CT-∆Σ also have a limited common-mode rejection ratio (CMRR) because of mismatch in the input resistors or input transconductance, which may limit the common-mode input range [9]....
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...The other coefficients 2 a , 3 a , 1 b and 2 b are optimized, using ∆Σ toolbox [9], to find a worst-case resolution of (>16 bits) for an input full scale slightly larger than 0....
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TL;DR: In this paper, a simulation technique for an adjacent channel leakage ratio (ACLR) of a class-S power amplifier (PA) with a delta-sigma modulator is proposed.
Abstract: A simulation technique for an adjacent channel leakage ratio (ACLR) of a class-S power amplifier (PA) with a delta-sigma modulator is proposed. This technique is based on three basic points. The first is a proper baseband signal, which must provide a fairly better ACLR than the target value of a PA as well as a tolerable total amount of time that can be handled by a transient circuit simulation. The second point is a carrier frequency adjustment for the observations free from spectrum leakage distortion due to a limited total amount of simulated time. The last is an ACLR calculation using only a steady-state output. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:462–465, 2014
2 citations
References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations