Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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01 Dec 2011
TL;DR: In this paper, a Delta Sigma Modulator (DSM) in form of MASH 2-1-2 was proposed to suppress the spurious tones in spectrum for all constant inputs with error feedback as dither.
Abstract: This paper presents a novel Delta Sigma Modulator (DSM) in form of MASH 2-1-2, which can suppress the spurious tones in spectrum for all constant inputs with error feedback as dither. As a finite-state machine (FSM), DSM always outputs a periodic sequence (or cycle) with a constant input. However, the novel DSM was designed to break up the periodic cycles and suppress quantization noise occurred in the fractional-N frequency synthesizer. Starting from the linear model of DSM, the principle of noise shaping was analyzed and logic implementation is introduced in detail. The performance is confirmed mathematically, by simulation, and experimental results.
2 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...The stochastic approach applied random dither signal to disrupt periodic cycles [5]....
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Posted Content•
TL;DR: In this paper, a 17-bit analogue-to-digital converter that incorporates mismatch and quantization noise-shaping techniques into an energy-saving 10-bit successive approximation quantiser is presented.
Abstract: This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noise-shaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB. We propose a novel fully-capacitive topology which allows for high-speed asynchronous conversion together with a background calibration scheme to reduce the oversampling requirement by 10x compared to prior-art. A 0.18 um CMOS technology is used to demonstrate preliminary simulation results together with analytic measures that optimise parameter and topology selection. The proposed system is able to achieve a FoMS of 183 dB for a maximum signal bandwidth of 15.6 kHz while dissipating 68 uW from a 1.8 V supply. A peak SNDR of 102 dB is demonstrated for this rate with a 0.201 mm^2 area requirement.
2 citations
TL;DR: In this paper, a short-word length implementation of the least mean square (LMS) algorithm was proposed to reduce the computational complexity of active noise control (ANC) systems.
Abstract: Active noise control (ANC) requires a controller with a small delay. However, in most ANC applications, this delay is significant due to the typically low sample rate, the anti-aliasing (AA), and reconstruction filters (RC) of the analog to digital (AD) and digital to analog (DA) converters. This delay can be reduced by increasing the sampling frequency at the expense of a significant increase in computational complexity. Sigma-delta AD and DA converters work at high sampling frequencies, but their use in ANC is limited due to the delay of AA and RC filters. This work proposes removing the AA and RC filters of the sigma-delta converters and using the oversampled signals directly in an ANC system. This proposal allows the ANC system to be implemented at a large sample frequency but using signals with fewer bits per sample (word-length). This is the first short-word length implementation of the least mean squares (LMS) algorithm to the authors’ knowledge. Gains of up to 6 times may be achieved in the computational complexity when compared with a long-word length implementation. Theoretical and simulation results validate the current solution.
2 citations
TL;DR: In this article, the role of band gap engineering in analyzing GAA-TFET using lattice-matched GaPSb and InP in the source region and channel/drain regions, respectively.
Abstract: Our focus is on the need for novel devices and the careful investigation of an electrically doped III–V ternary alloy-based gate-all-around tunnel field effect transistor (GAA-TFET) and its circuit applicability. We explored the role of band gap engineering in analyzing GAA-TFET using lattice-matched GaPSb and InP in the source region and channel/drain regions, respectively. This enhances DC and analog characteristics. The device features were then extracted using Silvaco and imported into a Cadence Virtuoso environment using the Verilog-A method to design a sigma delta ADC. The ADC output was then filtered and decimation using MATLAB, resulting into an 11-bit data converter with a 71.24-dB signal to-noise ratio.
2 citations
Dissertation•
15 Dec 2016
TL;DR: In this article, the authors propose a new capteur d'image for mobile en technologie CMOS (Complementary Metal Oxide Semiconductor) with 13Mpixels.
Abstract: Le travail de cette these vise la realisation d’un nouveau capteur d’images pour mobile en technologie CMOS (Complementary Metal Oxide Semiconductor). Ce capteur a ete developpe en vue de repondre a une forte demande du marche. Les prochaines generations de produits, necessitent des capteurs d’image avec des performances agressives. Par exemple, le niveau de qualite d’image peut etre fortement ameliore avec des architectures faible bruit, ou l’utilisation de nouvelles technologies, pour augmenter le niveau du signal ou diminuer la consommation. L’augmentation de la qualite d’image entraine un agrandissement de la taille des matrices de pixels, et de la resolution des donnees. La vitesse de conversion devient donc critique. Le sujet de cette these porte sur l’amelioration de ce dernier point. Une etude comparative a ete realisee pour etudier differentes architectures. Le convertisseur a rampe est le mieux adapte pour les petits pixels. Toutefois, son principal inconvenient est son temps de conversion qui necessite 2N cycles d’horloge. Afin d’obtenir un frame rate plus eleve, une methode tirant profit du bruit photonique a ete proposee. Ce circuit de lecture est fonde sur un convertisseur a rampe par morceaux, et un algorithme qui permet la linearisation des donnees. Afin de reduire le bruit, cette nouvelle architecture doit prendre en compte le double echantillonnage correle digital. Durant la periode de conception, des modes de test ont ete mis en place pour permettre la caracterisation du circuit. L’innovation se trouve dans le developpement d’une rampe par morceaux qui reduit le temps de lecture d’une ligne de 1us. Cependant, ce developpement a besoin d’une calibration adaptee. Un prototype de capteur d’image CMOS de 13Mpixel a ete fabrique en 65 nm, 5 niveaux de metaux, et 1 seul niveau de poly en technologie CMOS standard. Les mesures ont montre que l’INL et DNL du convertisseur etaient aussi performantes qu’avec une rampe lineaire classique. Une attention particuliere a ete apportee sur la mesure du bruit. Malheureusement, le bruit s’est montre plus eleve qu’avec un capteur « classique ». Cependant, la consommation reste identique en ayant une vitesse de conversion plus rapide. Les solutions proposees sont simples a integrer structurellement, et faciles a mettre en œuvre. Elles ont l’avantage de ne pas impacter la surface du pixel et preservent donc les performances de ce dernier. Les resultats issus des mesures sur silicium sont tres encourageants, car on obtient un gain de presque 20% sur le temps de lecture.
2 citations
References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations