Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
More filters
TL;DR: All-digital outphasing transmitter architecture using multidimensional power coding (MDPC) is proposed for noncontiguous concurrent multiband transmission with a high power efficiency.
Abstract: All-digital outphasing transmitter architecture using multidimensional power coding (MDPC) is proposed for noncontiguous concurrent multiband transmission with a high power efficiency. MDPC transforms multiband digital baseband signals into multibit low-resolution digital signals that drive switching-mode PAs. A prototype digital outphasing transmitter consists of two 1-GHz bandwidth GaN Class-D PAs and a Chireix power combiner. The two GaN PAs are driven by bipolar radio frequency (RF) pulse-width modulation (PWM) signals, which are transformed from a concurrent dual-band LTE signal by MDPC. The dual-band LTE signal with 15-MHz aggregate channel bandwidth at 240 and 500 MHz frequency band is transmitted with $-$ 30 and $-$ 37 dBc out-of-band emissions, respectively. Digital outphasing achieves more than two times higher coding efficiency than conventional concurrent dual-band digital transmitters with the same PAs in Class-S operation. Measured power coding efficiencies of 35.4% and 47.1% are observed with outphasing bipolar and 3-level RF PWM signals respectively, which are encoded from the dual-band LTE signal.
42 citations
TL;DR: This paper presents the first implementation results for a time-interleaved continuous-time DeltaSigma modulator, and the resulting modulator has only a single path of integrators, making it robust to DC offsets.
Abstract: This paper presents the first implementation results for a time-interleaved continuous-time DeltaSigma modulator. The derivation of the time-interleaved continuous-time DeltaSigma modulator from a discrete-time DeltaSigma modulator is presented. With various simplifications, the resulting modulator has only a single path of integrators, making it robust to DC offsets. A time-interleaved by 2 continuous-time third-order low-pass DeltaSigma modulator is designed in a 0.18-mum CMOS technology with an oversampling ratio of 5 at sampling frequencies of 100 and 200 MHz. Experimental results show that a signal-to-noise-plus-distortion ratio (SNDR) of 57 dB and a dynamic range of 60 dB are obtained with an input bandwidth of 10 MHz, and an SNDR of 49 dB with a dynamic range of 55 dB is attained with an input bandwidth of 20 MHz. The power consumption is 101 and 103 mW, respectively
42 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...Since no sampling is performed within the filters, the restriction of a maximum sampling frequency is only dependent on the regeneration time of the quantizer and the update rate of the DAC [2]....
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...Typically, continuous-time modulators are able to operate two to four times faster than their discrete-time counterparts, but with lower accuracy and linearity [2]....
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TL;DR: A novel low power compact loop filter using a single amplifier biquad (SAB) network is presented for continuous-time (CT) delta-sigma (ΔΣ) modulators that reduces power consumption and die area by minimizing the number of active elements and simplifying the modulator topology.
Abstract: A novel low power compact loop filter using a single amplifier biquad (SAB) network is presented for continuous-time (CT) delta-sigma (ΔΣ) modulators This new technique reduces power consumption and die area by minimizing the number of active elements and simplifying the modulator topology The new SAB network has a transfer function (TF) zero, which implements a local feedforward (FF) path in system-level diagram By having a local FF branch embedded in the SAB network, the FF branches to the summing block in the SAB based feedforward modulator topology is reduced to half the number of FF branches in the conventional topology Consequently, the SAB based modulator utilizes a switch-capacitor (SC) adder replacing the commonly used CT adder and the sample & hold blocks in the conventional architecture The SAB based loop filter with reduced FF branches simplifies the design and implementation of the high-order continuous-time ΔΣ modulator The proposed loop filter is a general filter, which can be used for both high and low oversampling ratios (OSRs) A 4th-order low pass continuous-time ΔΣ modulator is designed and implemented in 130 nm process to confirm the effectiveness of the proposed techniques Within a 72 MHz signal bandwidth, the measured dynamic range and SFDR of this prototype IC are 80 dB and 831 dB, respectively, and the total power consumption of 137 mW
40 citations
TL;DR: A wide-tuning-range low-power sigma-delta-based direct-RF-to-digital receiver architecture that improves jitter immunity to enable a high dynamic range, and, with a class-AB low-noise transconductance amplifier, guarantees a highly linear front end.
Abstract: A wide-tuning-range low-power sigma-delta-based direct-RF-to-digital receiver architecture is implemented in 65 nm CMOS. A flat signal transfer function is chosen to support wide-frequency-range radios. A multilevel (two-bit) nonreturn-to-zero DAC improves jitter immunity to enable a high dynamic range, and, with a class-AB low-noise transconductance amplifier, guarantees a highly linear front end. For a 4 MHz signal, the peak SNDR of the receiver exceeds 68 dB and is better than 60 dB across the 400 MHz to 4 GHz carrier frequency range. By virtue of utilizing a negative feedback digitizer close to the antenna, an IIP3 of +10 dBm is achieved while dissipating only 40 mW from 1.1 V/1.5 V supply voltages.
40 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...It has been reported in [12] that clock jitter perturbs the amount of feedback charge from the DAC and degrades the in-band SNR, but the actual mechanism by which clock jitter compromises the high-speed in-band performance has not been analyzed in detail....
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...This design, similar to [4], relies on current-mode integration sampling (CMIS) [17] to provide frequency translation within the loop....
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TL;DR: In this paper, a low-power noise-shaping ΔΣ time-to-digital converter (TDC) and its application to a fractional-N digital PLL is presented.
Abstract: This paper presents a low-power noise-shaping ΔΣ time-to-digital converter (TDC) and its application to a fractional-N digital PLL. With a simple structure of single-delay-stage Δ modulator followed by a charge pump based Σ modulator, a wide range of TDC input is converted to ΔΣ modulated single bit stream without loss of signal information. The ΔΣ architecture of TDC effectively improves the conversion performance of linearity and resolution while handling a large input range due to the operation of the dual-modulus divider. In addition, with a downscaling of the amount of the single delay in Δ modulator, the signal and noise transfer characteristics of TDC can be profiled to suppress the out-band noises at the input to the loop filter, resulting in easy filtering without any extra noise cancelling scheme. The DPLL is fabricated with a 0.13 μm CMOS technology. With a loop bandwidth of 1 MHz, DPLL shows an in-band phase noise of - 107 dBc/Hz at 500 kHz offset and an out-of-band phase noise of -118.5 dBc/Hz at 3 MHz offset. The TDC consumes 1 mA.
40 citations
References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations