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Understanding Delta-Sigma Data Converters

TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
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Proceedings ArticleDOI
11 Mar 2016
TL;DR: The paper presents an approach for design of sigma-delta (ΣΔ) converters that involves statistical and simulation based optimization techniques at different block levels and provides more resilience in the design and simulations of Σ� Δ modulators.
Abstract: The paper presents an approach for design of sigma-delta (ΣΔ) converters. This technique helps in finding the appropriate architecture and topology of ΣΔ modulator along with block level specifications. The design approach is implemented on the MATLAB/SIMULINK platform, that involves statistical and simulation based optimization techniques at different block levels. A 16-bit, 250 KHz signal bandwidth discrete-time switched capacitor ΣΔ converter is implemented using this technique. The behavioral model developed resulted in an ENOB of 15.58 bits, SNR of 105.9dB and third order distortion of −117.563dB. The technique besides saving time, provides more resilience in the design and simulations of ΣΔ modulators.

2 citations


Cites background or methods from "Understanding Delta-Sigma Data Conv..."

  • ...Conceptually, the Σ∆ converters employ oversampling and noise shaping techniques for low-resolution quantizers which result in high resolution and linearity....

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  • ...The model developed resulted in an effective number of bits (ENOB) of 15.58 bits, a signal to noise ratio (SNR) of 105.9dB, in-band noise (IBN) of -86.42dB and third order distortion (HD3) of - 117.563dB....

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Proceedings ArticleDOI
08 Aug 2017
TL;DR: This paper introduces a speed-enhanced incremental ADC architecture for high-resolution low-power sensor applications, incorporating a third-order sturdy MASH modulator, designed for a 0.35um CMOS process.
Abstract: This paper introduces a speed-enhanced incremental ADC architecture for high-resolution low-power sensor applications, incorporating a third-order sturdy MASH modulator Unlike previous sturdy MASH ADCs, owing to the properly modified loop filters in the 2-1 sturdy MASH, the quantization noise of the first noise-shaping loop could be cancelled out The proposed ADC with a 4b coarse SAR ADC and a 2-1 sturdy MASH modulator is designed for a 035um CMOS process Simulation result achieved an 18b resolution in conversion time of 606 us, consuming 161 uA current under a 33 V supply

2 citations


Cites methods from "Understanding Delta-Sigma Data Conv..."

  • ...In order to reduce the performance degradation of a high-order Multi-stAge noise-Shaping (MASH) architecture [6, 7], sturdy MASH (SMASH) architecture [8] can be chosen to eliminate the need for matching between analog and digital filter characteristics....

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Proceedings ArticleDOI
01 Oct 2008
TL;DR: This work presents the design and implementation of a decimation filter for an audio range DeltaSigma-modulator based on a dual wordlength multiply-accumulate (MAC) unit to handle the reduced wordlength of the input.
Abstract: In this work we present the design and implementation of a decimation filter for an audio range DeltaSigma-modulator. The architecture is based on a dual wordlength multiply-accumulate (MAC) unit to handle the reduced wordlength of the input. Each stage is composed of FIR filters which are mapped to the MAC unit. The design trade-offs and decisions for co-design of architecture and filters are discussed.

2 citations


Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...The ΔΣ-technique makes it possible to realize highresolution analog to digital converters (ADCs) without high precision analog components [1], [2]....

    [...]

Proceedings ArticleDOI
01 Jul 2018
TL;DR: The design and simulation results show that the target specification can be achieved by configuring the oversampling ratio and the digital filter according to the measurement bandwidth.
Abstract: This paper describes the design and simulation of a high order sigma-delta loop filter to use in a feedback loop for the QuADC project. The project target specifications required the selection of a fourth order feedback loop to achieve them. The design includes two loop rates (100 MHz and 20 MHz), and the selected loop was a cascade of integrators with feedforward topology. The simulation results show that the target specification can be achieved by configuring the oversampling ratio and the digital filter according to the measurement bandwidth.

2 citations


Additional excerpts

  • ...Sigma-Delta sampling relies on fast oversampling (OSR) with a resolution of a single or small number of bits and uses digital filtering to exchange resolution for bandwidth [1]....

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References
More filters
Journal ArticleDOI
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

399 citations

Journal ArticleDOI
James C. Candy1
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.

342 citations

Journal ArticleDOI
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

284 citations

Book ChapterDOI
James C. Candy1, O. Benjamin1
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.

255 citations

Journal ArticleDOI
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >

211 citations