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Understanding Delta-Sigma Data Converters

TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
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Proceedings ArticleDOI
01 Aug 2018
TL;DR: A new bitstream DAC architecture based on the sliding mode control of the output analogue filter model is introduced, optimized mainly to reproduce current transducer signals in power electronics (usually triangle waves), which can be done more accurately than traditional $\Sigma-\Delta$ solutions.
Abstract: The advances in FPGA technology have enabled to develop fast HIL (Hardware-in-the-Loop) simulators, revolutionizing control software and hardware development for power electronics. HIL simulators should reproduce the same analogue signals that could be measured on real main circuits. A very common limitation in these applications is the usable pin count of the FPGA, therefore using the most pin-effective Digital-to-Analogue Converters (DACs) becomes critical. $\Sigma-\Delta$ DACs provide a simple, FPGA-synthesizable solution using a single pin for each output, but the output signal's bandwidth and latency is usually not sufficient, because of the required analogue filters. Higher order $\Sigma-\Delta$ DACs usually perform much better in the aspect of the Signal-to-Noise-Ratio (SNR) but not the usable bandwidth. This paper introduces a new bitstream DAC architecture based on the sliding mode control of the output analogue filter model. It is optimized mainly to reproduce current transducer signals in power electronics (usually triangle waves), which can be done more accurately than traditional $\Sigma-\Delta$ solutions.

2 citations


Cites background or methods from "Understanding Delta-Sigma Data Conv..."

  • ...The converter is operated with much higher frequency than the Nyquist-frequency of the input signal, which is called oversampling [12]....

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  • ...The other useful feature is the guaranteed linearity [12], which is caused by the 1-bit DAC and the averaging method....

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  • ...There are many existing improvements of the Σ − ∆ DAC: higherorder and MASH-modulators [12] or sliding-mode control...

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  • ...There are many existing improvements of the Σ − ∆ DAC: higherorder and MASH-modulators [12] or sliding-mode control 978-1-5386-4198-9/18/$31.00 ©2018 IEEE 824 based approaches ([13], [14])....

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  • ...Using more bits naturally increases SNR and makes lower oversampling ratio possible but also reduces linearity [12]....

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Journal ArticleDOI
TL;DR: This paper presents an all-digital technique to control DC–DC switching buck converters for noise-sensitive low-power applications that adopts a unity-gain signal-transfer function delta-sigma modulator that avoids excess phase in the control loop.
Abstract: This paper presents an all-digital technique to control DC–DC switching buck converters for noise-sensitive low-power applications. The controller is designed based on a multi-sampling frequency digital delta-sigma modulator, whose sampling frequency is adjusted according to the load current. The proposed controller demonstrates the efficiency performance of the digital pulse-width modulation controller counterpart at heavy load while reducing output spikes by 37 dB without any additional processing. At light load, the controller scales down the switching frequency by scaling down delta-sigma modulator sampling frequency. Consequently, light-load efficiency is improved by more than 40% compared to its fixed frequency counterpart. In particular, the proposed solution adopts a unity-gain signal-transfer function delta-sigma modulator that avoids excess phase in the control loop. The proposed technique is compact, scalable and compatible with the standard digital CMOS implementation. Experimental and simulation results characterizing the proposed solution are provided.

2 citations

Journal ArticleDOI
TL;DR: This paper presents an enhanced dual-path delta-sigma analog-to-digital converter that employs not only doubly-differential structure to reduce common-mode errors in the system-level but also delayed-feed-in structure to mitigate the timing constraint of the feedback signal.
Abstract: This paper presents an enhanced dual-path delta-sigma analog-to-digital converter. Compared with other architectures, the enhanced architecture increases the noise shaping order without any instability problems and displays analog complexity equivalent to the multi-stage noise shaping architecture. Our delta-sigma converter is based on this new architecture. It employs not only doubly-differential structure to reduce common-mode errors in the system-level but also delayed-feed-in structure to mitigate the timing constraint of the feedback signal. Regarding the circuit implementation, the first-order enhancement of the quantization noise shaping is achieved via the use of a switched capacitor circuit technique. The circuit is incorporated into the active adder in a low-distortion structure. The supporting clock generation circuit that provides additional phases of clocks with the enhancement block is also implemented in the CMOS logic gates. A digital dynamic element matching circuit (i.e., segmented data-weighted-average circuit) is designed to reduce mismatch errors caused by the feedback DAC of modulator. A test chip, fabricated in a 0.18-μm CMOS process, provides a signal-to-noise+distortion ratio (SNDR) of 75-dB for a 1.0-MHz signal bandwidth clocked at 40-MHz. The 2nd harmonic is ―101 dB and the 3rd harmonic is ―94 dB when a ―4.5-dB 100-kHz input signal is applied.

2 citations

Dissertation
17 May 2019
TL;DR: In this paper, the design, modelling and characterisation of a charge-coupled device (CCD) camera imaging system and the prediction of the camera's performance in applications with Micro-Channel Plate (MCP) optics are discussed.
Abstract: This thesis is concerned with the design, modelling and characterisation of a ChargeCoupled Device (CCD) camera imaging system and the prediction of the camera’s performance in applications with Micro-Channel Plate (MCP) optics. The development and optimisation of analogue CCD readout electronics are described and its extension to a fully digital CCD readout method with its dedicated analogue front-end processing stage is presented. The mechanical and the optical design of the camera are presented and a performance model of the camera system from scintillator to detector is expressed by means of a system gain model. A noise mathematical model of the analogue chain of the CCD readout electronics is developed and compared to Spice simulations. A shaping filter method is proposed and implemented to generate noise time series from a given noise power spectral density. The method is adopted to build a time domain simulation model of the CCD camera system. The model allows investigation of the impact that different noise sources have on the performance of CCD readout methods and to drive the design criteria of the system. Characterisation of the CCD camera system by means of photon transfer curve theory is presented. Calibration of the system for X-ray detection, followed by the derivation of a quantitative model and relative comparison with real measurements in terms of scintillator light yields are presented. The resolution of the system is quantified by means of Modulation Transfer Function (MTF). A model of the performance of MCP optics is discussed and specific performance parameters such as gain and surface brightness are presented. An extension of their use for focusing neutrons is considered and the development of a neutron telescope concept using MCP optics for investigation of hydrogen distribution on a planetary surface at higher resolution that can be achieved with current instruments is presented.

2 citations

MonographDOI
15 Jan 2014
TL;DR: A number of state-of-the-art low power consuming digital delta-sigma modulator (ΔΣ) architectures for digital-to-analog converters (DAC) are presented in this thesis.
Abstract: A number of state-of-the-art low power consuming digital delta-sigma modulator (ΔΣ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ΔΣ DAC, the ...

2 citations

References
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Journal ArticleDOI
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

399 citations

Journal ArticleDOI
James C. Candy1
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.

342 citations

Journal ArticleDOI
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

284 citations

Book ChapterDOI
James C. Candy1, O. Benjamin1
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.

255 citations

Journal ArticleDOI
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >

211 citations