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Understanding Delta-Sigma Data Converters

Shanti Pavan, Richard Schreier, Gabor C. Temes
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
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Journal Article•DOI•
A 1.1 V 81.8 dB Delta-Sigma ADC

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Won-Tak Choi, Gil-Cho Ahn
31 Mar 2014-International Journal of Control and Automation
TL;DR: A 1.1 V 81.8 dB delta-sigma analog-to-digital converter (ADC) is presented and a successive approximation register (SAR) ADC is employed to function as both multi-bit quantizer and summing adder without using an additional amplifier.
Abstract: A 1.1 V 81.8 dB delta-sigma analog-to-digital converter (ADC) is presented. The split time integration technique for implementing multi-bit digital-to-analog converter (DAC) without using DEM has been developed and used. In order to reduce power consumption and area, a successive approximation register (SAR) ADC is employed to function as both multi-bit quantizer and summing adder without using an additional amplifier. The proposed deltasigma modulator operates at a 640 kHz clock rate and dissipates 850 W with a 1.1 V supply. It achieves 81.8 dB dynamic range (DR), 76.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth. The core area is 235 m 2 in a 45-nm CMOS technology.

1 citations

Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...Since the complexity of the AFE is affected by the resolution of the ADC, delta-sigma topology, which provides high dynamic range (DR) by using an oversampling and a noise shaping, is a well suited candidate for sensor interface [1]....

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Mixed-signal design technology for IoT radios

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Ming Ding
04 Dec 2019
TL;DR: The final author version and the galley proof are versions of the publication after peer review that features the final layout of the paper including the volume, issue and page numbers.
Abstract: • A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers.

1 citations

Cites methods from "Understanding Delta-Sigma Data Conv..."

  • ...Note that in the linearized model of the comparator, the gain g depends on the power of the overall signal (including the noise components) applied at the input of the comparator, as typically happens in the modelling of Sigma-Delta Modulators (SDM) [57]....

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  • ...57 4.6.1 Frequency detector . . . . . . . . . . . . . . . . . . . . . . . . 58 4.6.2 Chopped dynamic comparator . . . . . . . . . . . . . . . . . . 58 4.6.3 Digital loop filter . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.6.4 SDM DCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.7 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

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  • ...114 References 116 List of publications 125 Summary 129 Word of thanks 131 Biography 135 List of symbols and abbreviations Symbol Description Unit ACR Adjacent channel rejection ADC Analog to digital converter AMS Analog and mixed-signal BLE Bluetooth low energy BW Bandwidth Hz CMOS Complementary metal-oxide-semiconductor DAC Digital-to-analog converter DAL Dynamically-adjusted load DCO Digitally-controlled oscillator DCXO Digitally-controlled crystal oscillator DLF Digital loop filter DNL Differential non-linearity LSB DRC Design rule check DTC Digital-to-time converter ED Envelope detector ENOB Effective number of bits bit ERBW Effective resolution bandwidth Hz FCW Frequency control word FD Frequency detector FLL Frequency-locked loop FoM Figure of merit J/conversion-step FSM Finite-state machine fs Sampling frequency Hz FVC Frequency-to-voltage converter INL Integral non-linearity LSB IoT Internet-of-things LNA Low-noise amplifier LPWA Low-power-wide-area LUT Lookup table LVS Layout versus schematic LSB Least significant bit List of symbols and abbreviations 9 Symbol Description Unit MASH Multi-stage noise shaping MEMS Micro-electro-mechanical system MIM Metal-insulator-metal MOM Metal-oxide-metal MSB Most significant bit OP-AMP Operational amplifier PCB Printed circuit board PLL Phase-locked loop PMU Power-management-unit PN Phase noise ppm Parts per million P&R Place&route PTAT Proportional-to-absolute-temperature PVT Process voltage temperature RO Ring oscillator SAR ADC Successive approximation register ADC SDM Sigma delta modulator SFDR Spurious free dynamic range S&H Sample and hold SNR Signal to noise ratio SNDR Signal to noise and distortion ratio SoC System-on-chip SQNR Signal to quantization noise ratio TC Temperature coefficient TD Thermal-diffusivity TDC Time-to-digital converter VCO Voltage controlled oscillator Vfs Analog full scale amplitude V WSN Wireless sensor nodes XO Crystal oscillator 10 List of symbols and abbreviations Chapter 1 Introduction This chapter starts with an introduction of IoT applications....

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DOI•
On the design of stable, high performance sigma delta modulators

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Brett C. Hannigan
01 Jan 2018
TL;DR: The problem of designing sigma delta modulators with high performance and a clear indicator of the performance versus stability is addressed in this dissertation by developing a model of the sigmaDelta modulator that more accurately represents the system including robustness against the nonlinearities due to the quantizer element.
Abstract: The sigma delta architecture of analog-to-digital (A/D) converters is especially applicable to digitizing most bio-signals. High order single-bit sigma delta modulators provide high resolution and linearity with low circuit complexity but require careful design to avoid unstable states. Many existing methods of designing these systems have few degrees of freedom, rely extensively on simulations, and do not provide guarantees about stability. The problem of designing sigma delta modulators with high performance and a clear indicator of the performance versus stability is addressed in this dissertation. This is done by developing a model of the sigma delta modulator that more accurately represents the system including robustness against the nonlinearities due to the quantizer element. After introducing many stability criteria from literature, those most suited to design are identified and the model adjusted to allow these criteria to be applied. High performance is maintained by using the generalized Kalman-Yakubovič-Popov (GKYP) lemma to maximize noise rejection in the signal band using a semidefinite programming (SDP) framework that also permits the use of H∞, H2, and `1 norm-based stability constraints on the system. Several designs using this framework are presented and their relative merits discussed. Examples include an aggressive noise shaping design to compete with existing methods on the basis of performance and designs with guaranteed stability for a range of input signals. The performance-stability trade-off for the different stability constraints using this work is examined and motivated by simulation results.

1 citations

Journal Article•DOI•
A 2nd-Order ΔΣAD Modulator Using Dynamic Analog Components with Simplified Operation Phase

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Chunhui Pan1, Hao San1•
Tokyo City University1
01 Feb 2018-IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

1 citations

Cites background or methods from "Understanding Delta-Sigma Data Conv..."

  • ...The DWA logic circuit is designed to reduce the influence of the nonlinearities which occurred by the capacitors mismatch of the multi-bit DAC [3]....

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  • ...Multi-bit quantizer can also be chosen to relax the slew-rate requirement on the amplifier to reduce the power of the modulator [3]....

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  • ...On the other hand, the ∆ΣAD modulator reduces the quantization noise in the desired signal band by oversampling and noiseshaping technique, so that it is suitable to realize the high SNDR ADC in nanometer CMOS technology [3]....

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  • ...elements in a multi-bit digital-to-analog convertor (DAC) cause the harmonic distortion in the signal band, the dataweighted-averaging (DWA) logic circuit is applied to the ∆ΣAD modulator to reduce the influence of DAC nonlinearity errors [3]....

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Proceedings Article•DOI•
Band-pass ΔΣ D/A converter to up-convert frequency using images for wireless repeater

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K. Takei1•
Hitachi1
18 Mar 2011
TL;DR: In this paper, an over-sampling interpolator, image-selecting filter, and bandpass delta-sigma digital-to-analog converter (BPΔΣDAC) are proposed.
Abstract: I propose a new architecture of a frequency converting wireless repeater. The architecture consists of an over-sampling interpolator, image-selecting filter, and bandpass delta-sigma digital-to-analog converter (BPΔΣDAC). The BPΔΣDAC has functions both of noise-shaping and waveform equalizing to compensate for the difference between an impulse and a rectangular pulse. The proposed architecture achieves frequency up-converting of an input signal without an oscillator and a mixer; therefore it is effective in reducing the size, production cost, and design turn-around-time of the repeater.

1 citations

References
More filters
Journal Article•DOI•
A higher order topology for interpolative modulators for oversampling A/D converters

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K.C.-H. Chao1, S. Nadeem1, W.L. Lee1, C.G. Sodini1•
Massachusetts Institute of Technology1
01 Mar 1990-IEEE Transactions on Circuits and Systems
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

399 citations

Journal Article•DOI•
Decimation for Sigma Delta Modulation

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James C. Candy1•
Bell Labs1
01 Jan 1986-IEEE Transactions on Communications
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.

342 citations

Journal Article•DOI•
An analysis of nonlinear behavior in delta - sigma modulators

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Sasan H. Ardalan1, J.J. Paulos1•
North Carolina State University1
01 Jun 1987-IEEE Transactions on Circuits and Systems
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

284 citations

Book Chapter•DOI•
The Structure of Quantization Noise from Sigma-Delta Modulation

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James C. Candy1, O. Benjamin1•
Bell Labs1
01 Sep 1981-IEEE Transactions on Communications
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.

255 citations

Journal Article•DOI•
A fourth-order bandpass sigma-delta modulator

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S. Jantzi1, William Martin Snelgrove1, P.F. Ferguson2•
University of Toronto1, Analog Devices2
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >

211 citations

Related Papers (5)
Delta-sigma data converters : theory, design, and simulation

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01 Jan 1997
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01 Jan 1996
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02 Jan 1994
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01 Jan 1999
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01 Apr 1999-IEEE Journal on Selected Areas in Communications
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