Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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01 Dec 2013
TL;DR: This paper proves optimality of a class of Analog to Digital Converters, which can be viewed as generalized Delta-Sigma Modulators (DSMs), with respect to a performance measure that can be characterized as the worst-case average intensity of the signal representation error.
Abstract: In this paper we prove optimality of a class of Analog to Digital Converters (ADCs), which can be viewed as generalized Delta-Sigma Modulators (DSMs), with respect to a performance measure that can be characterized as the worst-case average intensity of the signal representation error. An analytic expression for the ADC performance is given. Furthermore, our result proves separation of quantization and control for this class of ADCs subject to some technical conditions.
1 citations
01 Jan 2008
TL;DR: In this article, a low-pass polyphase filter with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology is proposed and analyzed.
Abstract: This paper presents a strategy for successful polyphase-filter design for continuous-time quadrature band- pass sigma-delta modulators. Based on a low-pass filter with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology—which is suited for implementa- tion in low-power applications—analytical equations are derived. A new compensation scheme is proposed and implemented by cross-coupling additional resistors, without the necessity of extra-active components. Translation to intermediate frequency in second- and fourth-order polyphase filters with the proposed compensation scheme are compared to analytical considerations and simulation. Nonlinearities introduced by mismatch of feed- forward coefficients and finite gain-bandwidth of amplifiers are considered. Index Terms—Analog-digital conversion, chain of integrators with weighted capacitive feedforward summation (CICFF), chain of integrators with weighted feedforward summation (CIFF), complex filter, continuous-time (CT) circuit, polyphase filter, quadrature bandpass sigma-delta modulator.
1 citations
02 Dec 2013
TL;DR: A systematic design method is proposed to synthesize 3-2 MASH CT-ΔΣ modulators to achieve higher conversion bandwidths, BW ≥ 40MHz in a 130-nm CMOS technology.
Abstract: Continuous-time delta sigma (CT-ΔΣ ) ADCs are gaining wider adoption in data conversion systems primarily aided by their robustness to mismatch in nano-scale CMOS technologies and inherent anti-alias filtering. In past, several techniques have been employed to achieve wider conversion bandwidths by either scaling the designs to a lower technology node or by adopting architectures with lower oversampling ratios (OSR). Cascaded, or MASH, CT-ΔΣ ADCs have been explored to achieve conversion bandwidths by cascading lower order ΔΣ loops followed by a digital coarse quantization noise canceling filter (NCF). Another technique which has recently been explored is to increase the quantizer sampling rate, in a given technology node, by absorbing excess loop-delay (ELD) greater than one clock cycle (Ts) in the loop. However, these techniques individually cannot sufficiently meet the ever increasing bandwidth demand for the broadband wireless applications. Further, the ELD > Ts designs require an extra modulator order to achieve the same noise-shaping performance as the low-speed ELD <; 0.5 Ts prototype, necessitating high-order CT-ΔΣ loops. As a step towards combing the two techniques, we propose a systematic design method to synthesize 3-2 MASH CT-ΔΣ modulators to achieve higher conversion bandwidths, BW ≥ 40MHz in a 130-nm CMOS technology.
1 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...The NTFs for two loops are obtained using △Σ Toolbox [5]....
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...Cascaded, or MASH, CT-△Σ ADCs have been used to achieve conversion bandwidths by cascading lower-order △Σ loops followed by a digital coarse quantization noise canceling filter (NCF) [5]–[10]....
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...Further, cascaded △Σ modulators provide better noise-shaping performance than the single-loop modulators in lower OSR (OSR ≤ 8) designs [5], [6]....
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01 Dec 2008
TL;DR: In this paper, a comparison of incremental delta-sigma analog-to-digital converters for integrated temperature sensing applications is presented, where the modulator can be optimized for either accuracy or integrator signal excursion.
Abstract: This paper presents a comparison of incremental delta-sigma analog-to-digital converters for integrated temperature sensing applications. The characteristics of bipolar transistor based temperature sensing front-ends place specific requirements on the modulator loop architecture. Single loop delta-sigma architectures that removes the input signal from the internal loop by the addition of a feed-forward path to the quantiser, has been investigated thoroughly. It is found that the noise transfer function (NTF) implemented by the modulator can be optimised for either accuracy or integrator signal excursion, based on the requirements of the target application.
1 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...5 on the peak NTF magnitude is not absolute (Schreier and Temes, 2005)....
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...Now consider a more general form of second-order loop illustrated in Figure 4, known as a Cascade of Integrators FeedBack (CIFB) (Norsworthy et al., 1997; Schreier and Temes, 2005)....
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...A commonly used rule of thumb (Schreier and Temes, 2005) is to limit the maximum gain of the NTF to a suitable value, such as 1....
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Posted Content•
TL;DR: Under regularity assumptions on the input and the filtering kernel, it is proved for a second-order CT-$\Sigma\Delta$ that the error estimate may be in $o(1/N^2)$, where $N$ is the oversampling ratio.
Abstract: Continuous-time Sigma-Delta (CT-$\Sigma\Delta$) modulators are oversampling Analog-to-Digital converters that may provide higher sampling rates and lower power consumption than their discrete counterpart. Whereas approximation errors are established for high-order discrete time $\Sigma\Delta$ modulators, theoretical analysis of the error between the filtered output and the input remain scarce. This paper presents a general framework to study this error: under regularity assumptions on the input and the filtering kernel, we prove for a second-order CT-$\Sigma\Delta$ that the error estimate may be in $o(1/N^2)$, where $N$ is the oversampling ratio. The whole theory is validated by numerical experiments.
1 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...Such an 1-bit ADC operates at many times the Nyquist rate while achieving the same resolution of Nyquist modulators [2]....
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...Example of second-order ΣΔ modulator [2]...
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...These CT-ΣΔ modulators deliver more power-efficient operations than their discrete-time equivalent, as well as higher sampling rates [2, 7, 8]....
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References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations