Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
More filters
01 Jan 2009
TL;DR: The essential tool for this is the digital-to-analog converter (DAC), which is taken for granted that the stream of 16-bit digital information it contains can easily be made available to their ears in the analog world in which the authors live.
Abstract: Loading a CD player with one’s favorite CD has become an ordinary action. It is taken for granted that the stream of 16-bit digital information it contains can easily be made available to our ears, i.e., in the analog world in which we live. The essential tool for this is the digital-to-analog converter (DAC).
1 citations
01 Jan 2020
TL;DR: A third-order continuous-time sigma-delta modulator presented in this paper is constructed by adding a capacitor to the stable second-order low-pass RC filter to improve the quantization noise shaping and linearity of the modulator without increasing the power dissipation.
Abstract: FinFETs are known to be one of the promising devices for sub-50 nm regime. It involves better channel control, reduced short channel effects and low leakage current. A third-order continuous-time sigma-delta modulator presented in this paper is constructed by adding a capacitor to the stable second-order low-pass RC filter. It improves the quantization noise shaping and linearity of the modulator without increasing the power dissipation. A low-power, low-offset SR latch-based clocked comparator is used as quantizer. The designed modulator is implemented in FinFET 16 nm process, achieves the result of SNDR of 64 dB, ENOB of 10.5 bits, power dissipation of 48 µW and operating with 1 V supply voltage. It is suitable for low-power ADC in biomedical applications with a signal bandwidth of 4 kHz.
1 citations
24 May 2009
TL;DR: This paper studies the clock jitter error in multi-bit continuous-time Delta-Sigma modulators with non-return-to-zero (NRZ) feedback waveform and proposes a few useful formulas for the design of a less jitter sensitive NTF.
Abstract: This paper studies the clock jitter error in multi-bit continuous-time Delta-Sigma modulators with non-return-to-zero (NRZ) feedback waveform. It proposes a few useful formulas for the design of a less jitter sensitive NTF. The analytic results and MATLAB simulations show that in the design of an NTF, there is a trade-off between the in-band quantization noise and the jitter induced noise of the modulator.
1 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...The CLANS instruction of the Schreier toolbox is explained as follows [5, 6]: NTF = clans (order,OSR,Q,rmax) Order: The order of NTF....
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...Since in multi-bit modulators the maximum amplitude of the input signal is about ref V N Q N − [5, 6], so the maximum power of the input signal s P is calculated as follows:...
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...0 − + , therefore ) ( Δ n y belongs to a set as shown in relation (1) [5, 6]....
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Dissertation•
01 Jan 2015
TL;DR: In this paper, a digital input class D audio amplifier system which has the ability to reject the power supply noise and nonlinearly of the output stage is presented, and the main digital class D feed-forward path is using the fully-digital sigma-delta PWM open-loop topology.
Abstract: i ABSTRACT In this thesis, a digital input class D audio amplifier system which has the ability to reject the power supply noise and nonlinearly of the output stage is presented. The main digital class D feed-forward path is using the fully-digital sigma-delta PWM open-loop topology. Feedback loop is used to suppress the power supply noise and harmonic distortions. The design is using global foundry 0.18um technology. Based on simulation, the power supply rejection at 200Hz is about-49dB with 81dB dynamic range and-70dB THD+N. The full scale output power can reach as high as 27mW and still keep minimum-68dB THD+N. The system efficiency at full scale is about 82%. ii ACKNOWLEDGMENTS I would like to thank Professor Bertan Bakkaloglu for advising this project. I would also like to thank Professor Yu Cao and Hongjiang Song as committee members for my defense.
1 citations
TL;DR: In this paper, a transistor-level design of a continuous-time delta-sigma modulator with 150 MHz bandwidth in 28 nm CMOS process with 1.4/0.85 V supply is analyzed.
Abstract: This paper presents transistor-level design of a continuous-time delta-sigma modulator with 150 MHz bandwidth in 28 nm CMOS process with 1.4/0.85 V supply. Architectural-level design tradeoff for the high-speed and high-resolution requirement is analyzed. A stand-alone DAC calibration scheme is proposed for the linearization of the high-speed modulator. Simulation results show that the modulator achieves signal-to-noise-and-distortion ratio of 71 dB and spurious free dynamic range of 90 dB. The chip occupies 1.9 mm2 and consumes 213 mW.
1 citations
References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations