Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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24 May 2015
TL;DR: The proposed DPA utilizes a 1-bit second-order ΔΣ modulator to avoid nonlinearity problem of the multi-level quantization and achieve better quantization noise performance than the first-order modulator.
Abstract: This paper presents a ΔΣ modulated digital power amplifier (DPA) with a finite-impulse response (FIR) filter for wireless body area network (WBAN) applications. The proposed DPA utilizes a 1-bit second-order ΔΣ modulator to avoid nonlinearity problem of the multi-level quantization and achieve better quantization noise performance than the first-order modulator. The time-interleaving operation inherently provided by the embedded FIR filter mitigates the mismatching effect of PA cells. The proposed architecture not only improves the out-of-band noise performance but also reduces AM-AM and AM-PM distortions. The proposed ΔΣ DPA is implemented in 65nm CMOS. Simulation results show that it can achieve good out-of-band noise performance with the maximum output power of 6dBm and maximum power-added efficiency of 45%.
1 citations
TL;DR: An on-chip background half-range dithering-based calibration technique is proposed to improve the multi-bit feedback digital-to-analog converter matching, with limited overhead cost in terms of power consumption and area.
Abstract: This paper presents a continuous-time 4-0 MASH $\Delta \Sigma $ modulator with high power efficiency for wide-bandwidth wireless communication systems. An asynchronous successive-approximation-register (ASAR) is used as the quantizer in the $\Delta \Sigma $ modulator to reduce the power consumption and to cancel the comparator mismatch of the conventional flash quantizer. An on-chip background half-range dithering-based calibration technique is proposed to improve the multi-bit feedback digital-to-analog converter matching, with limited overhead cost in terms of power consumption and area. To alleviate the metastability error of the ASAR and to increase the bandwidth, a zero-order loop is added to further quantize the intrinsic quantization error of the ASAR. The design is fabricated in a 28-nm bulk CMOS process. Clocked at a frequency of 1.7 GHz, the modulator achieves 68.5-dB SNDR and 83.6-dB spurious-free dynamic range over an 85-MHz bandwidth, while consuming 23.9-mW power, leading to an excellent Walden figure-of-merit of 64.9 fJ/step and a Schreier figure-of-merit of 164 dB.
1 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...The ideal STF is simulated, using the Delta-Sigma toolbox provided by [15] and shown in Fig....
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...The MASH architecture avoids the stability considerations of high-order noise shaping and relaxes the requirements of the secondstage components [15]....
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TL;DR: It is shown that the period jitter of the output clock of the FLL due to stationary noise sources is cyclostationary and the F LL behaves as a time variant loop and there is translation of jitter frequency at the output.
Abstract: This paper presents a spectral analysis of period jitter of frequency-locked loops (FLLs) It is shown that the period jitter of the output clock of the FLL due to stationary noise sources is cyclostationary It is further shown that the FLL behaves as a time variant loop and there is translation of jitter frequency at the output These effects cannot be explained from the usual linear time invariant (LTI) models A $z$ -domain model of the FLL is presented and spectrum, power spectral density, and time averaged power of the single period and long term jitter are derived for various sources of noise in the FLL The results of the $z$ -domain model are compared with a computer model of the FLL made in MATLAB A comparison of the $z$ -domain model of the FLL and LTI models is presented and the limitations of LTI models are discussed in the light of the derived results
1 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...Thus, inputs to EC and DAC blocks are busy which satisfies the condition presented in [18] for qEC[n] and qDAC[n] to have white spectrum and the condition of being uncorrelated with their respective inputs....
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...The frequency and magnitude of tones of DSM are well analyzed in the literature [18] and this case is not discussed in this paper....
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01 Jun 2017
TL;DR: This study presents a single-loop, third-order, low-power, high-precision, switched-capacitor delta sigma modulator (DSM) for a portable electrocardiogram (ECG) acquisition device to improve signal-to-noise ratio (SNR) and reduce power consumption.
Abstract: This study presents a single-loop, third-order, low-power, high-precision, switched-capacitor delta sigma modulator (DSM) for a portable electrocardiogram (ECG) acquisition device. Several techniques, including modified feedforward structure, gain-enhanced current mirror operational transconductance amplifier (OTA), and dynamic comparator, are adopted to improve signal-to-noise ratio (SNR) and reduce power consumption. Simulation results indicate that the SNR and the corresponding effective number of bits are 100.8 dB and 16.45 bits, respectively, which fulfill the requirements of an ECG acquisition system. The circuit will be fabricated by the SMIC using a 0.18 µm general purpose process in the near future.
1 citations
Additional excerpts
...Compared with the CIFB structure, the CIFF structure decreases the output swing of integrators, thereby relaxing the design of the operational transconductance amplifier (OTA) and reducing harmonic distortion due to non-idealities [5]....
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25 Jul 2011
TL;DR: The conversion of arbitrary high order sigma-delta modulator Z-domain loopfilter transfer function into parallel form low order subsections in both S and Z domains is presented.
Abstract: In this paper we present the conversion of arbitrary high order sigma-delta modulator Z-domain loopfilter transfer function into parallel form low order subsections in both S and Z domains. The benefit of this type filter form representation is the existence of theory that can validate sigma-delta modulator's stability. The S domain filter representation is suitable for analog schematic element value calculation stage done according to the utilized transfer function when direct analogue parallel loopfilter implementation is performed.
1 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...Keywords—Sigma-Delta Modulators; Stability; Analog-toDigital Conversion I. INTRODUCTION Sigma-Delta modulators are the standard for analog to digital conversion nowadays (ADC) [1,2]....
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...INTRODUCTION Sigma-Delta modulators are the standard for analog to digital conversion nowadays (ADC) [1,2]....
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References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations