Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
More filters
TL;DR: The micropower operation, direct digital readout, and integration of electrical stimulation circuits make this interface ideally suited for closed-loop neuromodulation applications.
Abstract: We present a bidirectional neural interface with a 4-channel biopotential analog-to-digital converter (bioADC) and a 4-channel current-mode stimulator in 180 nm CMOS. The bioADC directly transduces microvolt biopotentials into a digital representation without a voltage-amplification stage. Each bioADC channel comprises a continuous-time first-order $\Delta \Sigma$ modulator with a chopper-stabilized OTA input and current feedback, followed by a second-order comb-filter decimator with programmable oversampling ratio. Each stimulator channel contains two independent digital-to-analog converters for anodic and cathodic current generation. A shared calibration circuit matches the amplitude of the anodic and cathodic currents for charge balancing. Powered from a 1.5 V supply, the analog and digital circuits in each recording channel draw on average $\text{1.54}\; \mu {\rm A}$ and $\text{2.13} \;\mu {\rm A}$ of supply current, respectively. The bioADCs achieve an SNR of $\text{58 dB}$ and a SFDR of ${>} \text{70 dB}$ , for better than 9-b ENOB. Intracranial EEG recordings from an anesthetized rat are shown and compared to simultaneous recordings from a commercial reference system to validate performance in-vivo . Additionally, we demonstrate bidirectional operation by recording cardiac modulation induced through vagus nerve stimulation, and closed-loop control of cardiac rhythm. The micropower operation, direct digital readout, and integration of electrical stimulation circuits make this interface ideally suited for closed-loop neuromodulation applications.
37 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...Data-weighted averaging is used for mismatch error shaping [19]....
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...However, this filter is approximately OSR times less effective at suppressing out of band quantization noise compared with an ideal filter [19]....
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...per two-fold OSR for a conventional first-order (counter) decimator or incremental ADC [19]....
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TL;DR: A reconfigurable sigma-delta modulator, which is able to support the predictable standards for the fourth generation (4G) of mobile communication systems, is presented in this paper.
37 citations
TL;DR: A new stage-sharing technique in a discrete-time (DT) 2-2 MASH delta-sigma (ΔΣ) ADC to reduce the modulator power consumption and chip die area is presented and other changes are introduced to improve the modulators dynamic range (DR) and power dissipation.
Abstract: This paper presents a new stage-sharing technique in a discrete-time (DT) 2-2 MASH delta-sigma (ΔΣ) ADC to reduce the modulator power consumption and chip die area. The proposed technique shares all active blocks between the two stages of the modulator. The 2-2 MASH modulator utilizes the second-order Chain of Integrators with Weighted Feed-forward Summation (CIFF) and the Cascade of Integrators with Distributed Feedback Branches (CIFB) architectures for the first and second stages, respectively. Using the proposed technique, the second integrator and the adder op-amps of the modulator first stage are shared with the first and second integrator op-amps of the second stage. In addition to the stage-sharing scheme, other changes are introduced to improve the modulator dynamic range (DR) and power dissipation. Measurement results show that the modulator designed in a 0.13 μm CMOS technology achieves 75 dB SNDR over a 5 MHz signal bandwidth with a clock frequency of 130 MHz, while dissipating less than 9 mW analog power.
37 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...However, this may endanger the modulator stability in a single loop configuration [5]....
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...The total input-referred thermal noise of the first integrator is [5]...
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...One option to increase the modulator overall order and still maintain stability is to use a multistage-noise-shaping (MASH) delta-sigma modulator [5]....
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...However, the MASH is vulnerable to mismatch effects [5]....
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...Since the low-distortion architecture is embedded in the first stage using the feedforward pass from the input to the adder block, the input signal does not travel through the first and second integrators [5]....
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Proceedings Article•
01 Jan 2006
TL;DR: In this paper, a quadrature bandpass ΔΣ ADC for a multistandard TV tuner achieves a total dynamic range of 90 dB over an 8.5-MHz passband centered on 44 MHz while consuming 375 mW.
Abstract: A quadrature bandpass ΔΣ ADC for a multistandard TV tuner achieves a total dynamic range of 90 dB over an 8.5-MHz passband centered on 44 MHz while consuming 375 mW. The fourth-order continuous-time ADC uses active-RC resonators configured in a modified feedforward architecture.
37 citations
TL;DR: This paper describes an energy-efficient bridge readout IC (ROIC), which consists of a capacitively coupled instrumentation amplifier that drives a continuous-time delta–sigma modulator (CT) and a digital to analog converter (DAC) to increase the CCIA’s useful dynamic range.
Abstract: This paper describes an energy-efficient bridge readout IC (ROIC), which consists of a capacitively coupled instrumentation amplifier (CCIA) that drives a continuous-time delta–sigma modulator (CT $\Delta \Sigma \text{M}$ ). By exploiting the CCIA’s ability to block dc common-mode voltages, the bridge’s bias voltage may exceed the ROIC’s supply voltage, allowing these voltages to be independently optimized. Since bridge output is typically much smaller than bridge offset, a digital to analog converter (DAC) is used to compensate this offset before amplification and thus increase the CCIA’s useful dynamic range. Bridge loading is reduced by using a dual-path positive feedback scheme to boost the CCIA’s input impedance. Furthermore, the CCIA’s output is gated to avoid digitizing its output spikes, which would otherwise limit the ROIC’s linearity and stability. The ROIC achieves an input-referred noise density of 3.7 nV/ $\surd $ Hz, a noise efficiency factor (NEF) of 5, and a power efficiency factor (PEF) of 44, which both represent the state of the art. A pressure sensing system, built with the ROIC and a differential pressure sensor (AC4010), achieves 10.1-mPa ( $1\sigma$ ) resolution in a 0.5-ms conversion time. The ROIC dissipates about 30% of the system’s power dissipation and contributes about 6% of its noise power. To reduce the sensor’s offset drift, a temperature compensation scheme based on an external reference resistor is used. After a two-point calibration, this scheme reduces bridge offset drift by $80\times $ over a 50 °C range.
37 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...SNRjgate determined by this jitter is given by [27]...
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References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations