Open AccessBook
Understanding Delta-Sigma Data Converters
Reads0
Chats0
TLDR
This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.Abstract:
Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.read more
Citations
More filters
Journal ArticleDOI
A low power accelerometer system with hybrid signal output
Yan Liu,Lulu Zhang,Beibei Wang +2 more
TL;DR: A low power micromechanical capacitive accelerometer system is presented with hybrid signal output in this paper, andCorrelated-doublesample (CDS) technique is utilized in the front end circuit to ensure low noise output signal.
Journal ArticleDOI
Analysis and Calibration for Wideband Times-2 Interleaved Current-Steering DACs
Daniel Beauchamp,Keith M. Chugg +1 more
TL;DR: An analytical model is developed for the interleaving and data timing errors that are encountered in modern times-2 interleaved digital-to-analog converters with a current-steering (CS) architecture and a calibration algorithm is proposed that treats all of them.
Proceedings ArticleDOI
A study of soft switching dc-dc converter under delta-sigma modulation
Atsushi Hirota,Mutsuo Nakaoka +1 more
TL;DR: In this paper, a soft switching type dc-dc converter was proposed to suppress noise levels, and a reformed delta-sigma modulation circuit was introduced to reduce switching loss, and the proposed converter also introduced soft switching technique.
Parallel Sigma-Delta ADC Structures D ensity Parity Check Code Decoders and Low Complexity Techniques for Low
TL;DR: In this thesis, contributions are made in the area of receivers for wireless communication standards, focusing on implementations of forward error correction using low-density parity-check (LDPC) codes, and highbandwidth analog-to-digital converters (ADC) using sigma-delta modulators.
Proceedings ArticleDOI
Programmable reference for power-aware DVS
TL;DR: Experimental results show that the linear range of voltage is obtained and the step response between 0.9 and 1.2 V is equal to 1.5 µs, thus validating the functionality of the mixed-level model and further verification is found by the experimental results being equivalent to the simulation results.
References
More filters
Journal ArticleDOI
A higher order topology for interpolative modulators for oversampling A/D converters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Journal ArticleDOI
Decimation for Sigma Delta Modulation
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Journal ArticleDOI
An analysis of nonlinear behavior in delta - sigma modulators
Sasan H. Ardalan,J.J. Paulos +1 more
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Book ChapterDOI
The Structure of Quantization Noise from Sigma-Delta Modulation
James C. Candy,O. Benjamin +1 more
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Journal ArticleDOI
A fourth-order bandpass sigma-delta modulator
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.