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Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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25 Apr 2017
1 citations
01 Jan 2015
TL;DR: In this article, a hybrid CT/DT delta sigma interface for micro electro mechanical accelerometer, which is located in the negative feedback, is presented, where the accelerometer with natural continuous time property is considered as the first stage of the modulator while a discrete time integrator is used as the second stage to take the advantages of CT and DT delta sigmoid sigma simultaneously.
Abstract: A novel hybrid CT/DT delta sigma interface for micro electro mechanical accelerometer, which is located in the negative feedback, is presented in this article. The accelerometer with natural continuous time property is considered as the first stage of the modulator while a discrete time integrator is considered as the second stage of hybrid delta sigma to take the advantages of CT and DT delta sigma, simultaneously. The continuous time delta sigma modulator makes the use of inherent anti-aliasing filter and increased sampling frequency. While the discreet time delta sigma modulator benefits from the high accuracy of implementation. MATLAB simulation of the proposed hybrid delta sigma indicates the Signal to Noise plus Distortion Ratio (SNDR) of 114 dB over 1 KHz bandwidth when Over Sampling Ratio (OSR) is 256.
1 citations
26 Jun 2011
TL;DR: In this article, a new coefficient scaling technique is proposed to determine the dynamic range of the integrators of sigma delta modulators, which relies on numerical optimization of the interstage coefficients to minimize a multi-criteria objective function taking into account the sum of capacitor values implementing the modulator and the voltage swing at each integrator output, for a given target SNR.
Abstract: This paper presents a new coefficient scaling technique to determine the dynamic range of the integrators of sigma delta modulators. This technique relies on numerical optimization of the interstage coefficients to minimize a multi-criteria objective function taking into account the sum of capacitor values implementing the modulator and the voltage swing at each integrator output, for a given target SNR. The optimization process includes the effect of thermal noise at each integrator stage. A user-defined parameter can steer the optimization process priority towards either the size of the capacitors or the integrators output voltage swing, depending on the given application.
1 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...A common procedure for designing a sigma-delta (ΣΔ) modulator involves synthesizing the desired noise transfer function (NTF) ans signal transfer function (STF) to attain a required signal-to-quantization-noise ratio (SQNR) for a given oversampling ratio (OSR) [1]....
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...The modulator was designed for an OSR of 64 and a 3-bit quantizer....
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...Generally [1], the dominant source is the thermal noise of the input stage....
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...I. INTRODUCTION A common procedure for designing a sigma-delta (ΣΔ) modulator involves synthesizing the desired noise transfer function (NTF) ans signal transfer function (STF) to attain a required signal-to-quantization-noise ratio (SQNR) for a given oversampling ratio (OSR) [1]....
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...With an OSR of 64, the resonator coefficients g values are 0.0013 and 0.0016....
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29 Nov 2011
TL;DR: A novel mixed-signal feedback technique using a sigma-delta ADC has been proposed wherein the digital signal is scaled, integrated and fed back to the previous analog stage, which is an improvement of 3 bits over existing techniques.
Abstract: Cardiovascular diseases are leading cause of deaths worldwide. With increasing graying population and limited health infrastructure there is a need for portable and implantable ECG devices to diagnose these diseases early on. In general an ECG device requires three or more electrodes, which need to be applied to the body via a gel, to obtain a satisfactory reading. This puts a constraint on the portability of the device. This thesis deals with designing a fully-integrated 10 bit analog front-end i.e. an instrumentation amplifier and an ADC, specifically, for a two-electrode ECG device. Integrated ECG read-out circuits have to deal with two challenges mainly viz. obtaining a high common-mode rejection ratio (CMRR) and integrating large time-constants on the chip. Firstly, all sources of interference which affect an ECG reading is studied. It is shown that for a portable and integrated read-out circuit, a high CMRR is obtained from the fact that the device will be floating and hence the circuit itself need not have a high CMRR. Existing techniques for integrating large time-constants are presented and compared. It is shown that these techniques either give rise to unpredictable time-constants and are non-linear near the required cut-o frequency or consume a lot of power from a system perspective. A novel mixed-signal feedback technique using a sigma-delta ADC has been proposed wherein the digital signal is scaled, integrated and fed back to the previous analog stage. The advantages of such a method are more control over the position of the cut-o frequency and higher linearity. The power consumption needed to implement such a technique is negligible. The circuit is designed in CMOS 0.35um I3T25 technology. The designed instrumentation amplifier reports the best SNR and 3rd highest Noise-Efficieny Factor (NEF). The linearity at the cut-o frequency is shown to be of 10 bits which is an improvement of 3 bits over existing techniques. The total static power consumption for the system is 66uW. The implementation of the time-constant consumes only 40nW of static power.
1 citations
TL;DR: This paper presents a third order continuous time current mode ΣΔ modulator for WLAN 802.11b standard applications and proposes a modified cascade current mirror integrator with reduced input impedance which results in more bandwidth and linearity and hence improves the dynamic range.
1 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...Hence, choosing of the third order modulator is more reasonable which requires OSR of 10 and therefore the sampling rate of 400 MHz, a much simpler value to be achieved....
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References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations