Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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20 May 2012
TL;DR: This paper presents transistor-level design of a continuous-time (CT) reconfigurable ΔΣ modulator in a 1.2 V 65 nm CMOS process that achieves signal-to-noise-and-distortion-ratio (SNDR) and power consumption over all bandwidths.
Abstract: This paper presents transistor-level design of a continuous-time (CT) reconfigurable ΔΣ modulator in a 1.2 V 65 nm CMOS process. Both architectural- and circuit-level power-optimization techniques, such as flexible loop order and quantizer bit, switchable OTA unit cells, and folding flash ADC, are utilized to achieve power efficiency over all bandwidths. As gate leakage current in 65 nm technology becomes prominent, a DAC biasing scheme that is robust to gate leakage current is employed. Simulation results show that the modulator achieves signal-to-noise-and-distortion-ratio (SNDR) of 73.3/76.5/77.4/84.4 dB for 20/10/3/0.5 MHz bandwidth (BW) with power consumption of 23.9/20.7/9.49/7.22 mW, respectively. The respective figure of merit (FOM) equals 0.16/0.19/0.26/0.53 pJ/conv.
1 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...The number of the quantizer bit is maintained larger than that of the loop order by at least one to ensure a stable input range of -6dBFS without sacrificing the NTF [8]....
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...Hence, the gain-bandwidthproduct (GBW) limitation of the first OTA (OTA1) has the least impact among all OTAs on the noise transfer function (NTF) [5] and therefore the signal-to-quantization-noise-ratio (SQNR)....
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15 Apr 2013
TL;DR: This paper presents a 3rd order 1.5-bit Continuous-Time Fully Differential ΣΔ modulator with distributed feedback for a class D audio amplifier, using BJT differential pairs to implement the integrator stages.
Abstract: This paper presents a 3rd order 15-bit Continuous-Time Fully Differential ΣΔ modulator with distributed feedback for a class D audio amplifier, using BJT differential pairs to implement the integrator stages By relying on simple gain blocks instead of operational amplifiers to build the loop filter, a simpler overall circuit is obtained, where the non-ideal effects are embedded in the loop filter transfer function This leads to a more difficult design process for the loop filter circuit, solved through the use of an optimization procedure based on genetic algorithms Simulations of the electrical circuit show that it is capable of achieving a SNDR value of 734 dB and THD+N of about -80 dB for a signal bandwidth of 20 kHz and a sampling frequency of 128 MHz
1 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...Sigma-Delta modulators (Ʃ∆Ms) poise themselves as the best option for low frequency, highresolution applications, given their native linearity, robust analog implementation and reduced anti-aliasing filtering requirements [2], [3]....
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11 Nov 2010
TL;DR: Four architectures are analyzed as candidate DACs for a fully differential (FD), GSM, SDM design and the advantages of an FD Charge redistribution DAC (CDAC) topology that uses individual level averaging (ILA) as DEM are highlighted.
Abstract: Multi-bit ΣΔ modulators have become the preferred option for high performance, low power cellular GSM applications. When using multi-bit quantization, modulator performance becomes extremely sensitive to the internal digital-to-analog converter (DAC) non-linearity. DAC designs must fulfill linearity, power, and speed requirements for GSM while at the same time enabling dynamic element matching (DEM) techniques to further alleviate linearity problems. In this paper, four architectures are analyzed as candidate DACs for a fully differential (FD), GSM, SDM design. Our analysis highlights the advantages of an FD Charge redistribution DAC (CDAC) topology that uses individual level averaging (ILA) as DEM. Simulations favor a CDAC architecture mainly because it provides the best speed/power/linearity compromise. Evaluations of a complete modulator design using the proposed FD CDAC topology were performed, showing that no in-band harmonic distortion is present in the modulator output.
1 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...The second is by using a modulator order greater than two, and the third is by using multi-bit quantization [1], [2]....
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Dissertation•
01 Oct 2009
TL;DR: University of Minnesota M.S. thesis: “Electrical and Computer Engineering: Towards a post-modern view of reinforcement learning and artificial intelligence”.
Abstract: University of Minnesota M.S. thesis. October 2009. Major: Electrical and Computer Engineering. Advisor: Dr. Hua Tang. 1 computer file (PDF); viii, 48 pages. Ill. (some col.)
1 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...It has been studied that pulse position jitter may be regarded insignificant due to noise shaping and high loop gain of the modulator [2],[3],[4]....
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...Oversampling will not reduce the amount of total quantization noise, but it will spread the noise across a larger frequency spectrum so that the power of in-band quantization noise is reduced [1],[2],[3],[4],[5]....
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...Pulse width jitter is not noise shaped and any error is directly fed back to the input, which seriously degrades the performance of CT delta-sigma modulators [2],[3],[4]....
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...A delta-sigma modulator consists of three main components: a loop filter (or loop transfer function H(z)), an analog-to-digital converter (or a clocked quantizer), and a feedback digital-to-analog converter (DAC) [2],[3],[4],[5]....
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...2 Noise Shaping Technique Noise shaping is further used to reduce the noise power in the signal band [1],[2],[3], [4],[5]....
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01 Jan 2019
TL;DR: A rigorous proof is provided that the Igelnik and Pao construction is a universal approximator for continuous functions on compact domains, with \(\varepsilon\)-error convergence rate inversely proportional to the number of network nodes; this result is extended to the non-asymptotic setting using a concentration inequality for Monte-Carlo integral approximations.
Abstract: Author(s): Nelson, Aaron Andrew | Advisor(s): Saab, Rayan | Abstract: We study two problems from mathematical signal processing. First, we consider problem of approximately recovering signals on a smooth, compact manifold from one-bit linear measurements drawn from either a Gaussian ensemble, partial circulant ensemble, or bounded orthonormal ensemble and quantized using \(\Sigma\Delta\) or distributed noise-shaping schemes. We construct a convex optimization algorithm for signal recovery that, given a Geometric Multi-Resolution Analysis approximation of the manifold, guarantees signal recovery with high probability. We prove an upper bound on the recovery error which outperforms prior works that use memoryless scalar quantization, requires a simpler analysis, and extends the class of measurements beyond Gaussians.Second, we consider the problem of approximation continuous functions on compact domains using neural networks. The learning speed of feed-forward neural networks is notoriously slow and has presented a bottleneck in deep learning applications for several decades. For instance, gradient-based learning algorithms, which are used extensively to train neural networks, tend to work slowly when all of the network parameters must be iteratively tuned. To counter this, both researchers and practitioners have tried introducing randomness to reduce the learning requirement. Based on the original construction of B.~Igelnik and Y.H.~Pao, single layer neural-networks with random input-to-hidden layer weights and biases have seen success in practice, but the necessary theoretical justification is lacking. We begin to fill this theoretical gap by providing a (corrected) rigorous proof that the Igelnik and Pao construction is a universal approximator for continuous functions on compact domains, with \(\varepsilon\)-error convergence rate inversely proportional to the number of network nodes; we then extend this result to the non-asymptotic setting using a concentration inequality for Monte-Carlo integral approximations. We further adapt this randomized neural network architecture to approximate functions on smooth, compact submanifolds of Euclidean space, providing theoretical guarantees in both the asymptotic and non-asymptotic cases.
1 citations
References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations