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Understanding Delta-Sigma Data Converters

TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
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Patent
18 Mar 2014
TL;DR: In this paper, an analogue-digital converter (5) having at least one input, to which one analogue input signal (S(t)) can be supplied, and one output (31), which is configured to output a digital data stream that represents the analogue input signals, was defined, where the output stage (3) is designed to select the output signal of the analog-digital converters (21a, 21b) that lies inside a specifiable range of amplitude and has a greater than specifiable adjacent output signal.
Abstract: The invention relates to an analogue-digital converter (5) having at least one input, to which at least one analogue input signal (S(t)) can be supplied, and at least one output (31), which is configured to output a digital data stream that represents the analogue input signal, wherein the analogue-digital converter has an optical input stage (1), which is designed to convert the analogue input signal (S(t)) into a phase-modulated optical signal and to feed the signal to a hybrid coupler (12) having a plurality of output waveguides (122), each connected to at least one photodiode (13a, 13b), the connection contacts of the photodiodes (13a, 13b) are each connected to the input of an associated analogue-digital converter (21a, 21b), with which converters an analogue electrical input signal can be converted into a digital electrical output signal and the output of the analogue-digital converters (21a, 21b) is connected to the inputs of an output stage (3), which is designed to form the digital data stream at the output (31) from the digital output signals of the analogue-digital converters (21a, 21b), wherein the output stage (3) is designed to select the output signal of the analogue-digital converter (21a) that lies inside a specifiable range of amplitude and has a specifiable slope and/or is greater than specifiable adjacent output signal. The invention further relates to a corresponding method for generating a digital data stream.
Proceedings ArticleDOI
28 May 2022
TL;DR: In this paper , the authors present an analysis of the factors influencing the ISG and propose measures to maximize the inter-stage gain in a 0-X MASH modulator.
Abstract: The performance of a 0-X MASH DSM is primarily defined by the DSM noise-shaping and the inter-stage gain (ISG). Due to system specification like modulator order and OSR, the DSM noise shaping is limited. All further performance in the 0-X MASH modulator is achieved by setting a large ISG, which amplifies the residue signal before it is processed by the fine stage DSM. This paper presents an analysis of the factors influencing the ISG and proposes measures, which can be used to maximize it. Most importantly, it is shown, that the CIFB DSM architecture is preferred, since the wideband residue overloads the CIFF architecture with its peaking OOB STF much earlier, thus CIFB results in more ISG and less internal swings. The presented analysis can be used as a guideline for achieving optimum performance in a 0-X MASH DSM and yielding the maximum SQNR.
Journal ArticleDOI
TL;DR: In this paper , the authors proposed a robust and highly efficient digital predistortion (DPD) concept for the linearization of wideband RF power amplifiers (PAs), which is based on the combination of a parallelized delta-sigma modulator (DSM) and a forward model of the PA.
Abstract: In this article, we propose a new robust and highly efficient digital predistortion (DPD) concept for the linearization of wideband RF power amplifiers (PAs). The proposed approach is based on the combination of a parallelized delta-sigma modulator (DSM) and a forward model of the PA. This concept applies multi-rate techniques on a DSM that incorporates the forward PA model in its feedback loop to perform the required signal predistortion. Such a technique eliminates the need of reverse modeling and its associated problems. The multi-rate approach relaxes enormously the clock speed requirement of the DPD, which allows handling high signal bandwidths at feasible sampling rates. Moreover, enhanced performance can be achieved without the need of increasing the order of the modulator which reduces the sensitivity of the system to gain variations and phase distortions caused by the nonlinear PA characteristics. Three time-interleaved parallel DPD (P-DPD) variants are described and introduced, all of them have been shown to offer increased accuracy, and consequently better linearization performance compared to the DSM-based DPD state-of-the-art. The proposed architectures are tested and assessed using extensive real-world RF measurements at the 3.6 GHz band utilizing wideband 100 MHz 5G New Radio (NR) transmit waveforms, evidencing excellent transmit signal quality.
01 Jan 2011
TL;DR: A new interpolation technique using extra samples instead of zeros resulting from the oversampling of the input signal is proposed which not only reduces the die area and the order of the anti-alias filter but also improves A/D converter performance.
Abstract: Time interleaved sigma-delta converter is a potential candidate for multi-mode wideband analog to digital (A/D) converters dedicated for multistandard receivers. However, the interpolation by zeros to compress the useful signal bandwidth at the input of the sigma-delta modulator imposes constraints on the implementation of the analog part leading to a very large die area due to the high value required for the sampling capacitor. This paper proposes a new interpolation technique using extra samples instead of zeros resulting from the oversampling of the input signal. This new technique not only reduces the die area and the order of the anti-alias filter but also improves A/D converter performance. The proposed technique was simulated and implemented in a four channel time inter- leaved sigma-delta designed in a 1.2 V 65 nm CMOS process.

Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...Sigma-delta (RD) converters [3] are good candidates to achieve high resolution conversion but their bandwidth is very narrow compared to the requirements needed for software radio applications....

    [...]

Journal ArticleDOI
TL;DR: This article presents a continuous-time (CT) delta–sigma capacitance-to-digital converter (CDC) intended for use in applications with high capacitance resolution (tens of aF), and a large parasitic capacitance.
Abstract: This article presents a continuous-time (CT) delta–sigma ( $\Delta \Sigma $ ) capacitance-to-digital converter (CDC) intended for use in applications with high capacitance resolution (tens of aF), and a large parasitic capacitance ${C}_{P}$ ( $>$ 400 pF). It consists of a current conveyor (CC) front-end and a CT $\Delta \Sigma $ modulator. The CC-based front-end isolates ${C}_{P}$ from the first integrator of the modulator, and the CC’s output current is directly coupled to the CT $\Delta \Sigma $ modulator. The CC uses a class-AB configuration, which enables to maintain energy efficiency and its capacitance resolution even with ${C}_{P}$ . The proposed CDC is fabricated in a 110-nm CMOS process and occupies only 0.033 mm2. It achieves a capacitance resolution of 21.5–59 aF with an input range of 0.2–1.5 pF. This corresponds to an effective resolution of 14.3 bits in a conversion time of 1.2 ms, while drawing only 120 $\mu \text{W}$ from a 1.5-V supply. It also achieves a capacitance resolution of 119.4 aF with ${C}_{P}$ of 480 pF, offering robust capacitance resolution with external noise interference (10 ${V}_{\text {PP}}$ ).
References
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Journal ArticleDOI
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

399 citations

Journal ArticleDOI
James C. Candy1
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.

342 citations

Journal ArticleDOI
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

284 citations

Book ChapterDOI
James C. Candy1, O. Benjamin1
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.

255 citations

Journal ArticleDOI
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >

211 citations