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Understanding Delta-Sigma Data Converters

TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
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Journal ArticleDOI
TL;DR: A discrete-time bandpass modulator using the noise-coupling technique that only needs to a second- order loop filter to have asecond-order noise shaping and reduces the power consumption, area, and nonlinearity of the modulator.
Abstract: In bandpass modulators, a 2N-order loop filter can lead to an N-order noise shaping in the band of interest. This caused a bandpass modulator with more complex structure than a lowpass modulator and increased the power consumption and area of the modulator. In this paper, we proposed a discrete-time bandpass modulator using the noise-coupling technique that only needs to a second- order loop filter to have a second-order noise shaping. To realize a noise coupled bandpass modulator, we need to implement Z -2 delay block in the analog domain, but the proposed modulator uses only Z -1 delay blocks to apply the noise coupling technique. This simplifies the structure of the modulator and reduces the power consumption, area, and nonlinearity of the modulator. The error in the coupling path is considered and the effect of it on the modulator resolution is analyzed. According to the simulation results, the proposed modulator results in SNR = 84.9 dB at 80 MHz sampling frequency, 200 KHz bandwidth and OSR = 200.

Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...It is caused more power consumption but the proposed modulator has advantage of zero optimization [2]....

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  • ...If the quantization noise is coupled to the modulator input, the noise coupled architecture would have been very sensitive to the coupling path errors [2]....

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DOI
21 May 2023
TL;DR: In this article , finite impulse response (FIR) feedback in low-pass delta-sigma modulators was investigated to improve loop filter linearity and reduce the sensitivity of the modulator to clock jitter.
Abstract: This paper investigates finite impulse response (FIR) feedback in bandpass delta-sigma modulators (BP-$\Delta \Sigma \text{Ms}$). FIR feedback in lowpass delta-sigma modulators (LP-$\Delta \Sigma \text{Ms}$) improves loop filter linearity and reduces the sensitivity of the modulator to clock jitter. We show that similar benefits can be obtained in a BP-$\Delta \Sigma \mathrm{M}$ if the FIR filter in the feedback path is made a bandpass one11This work was supported in part by Grant PID2019-103876RB-I00, funded by MCIN/AEI/10.13039/501100011033, by the European Union ESF Investing in your future, and by “Junta de Andalucía” under Grant P20-00599 and in part by the Center of Excellence in RF, Analog and Mixed-Signal ICs (CERAMIC), IIT Madras..
Proceedings ArticleDOI
28 May 2022
TL;DR: In this paper , a hybrid CT/DT0-2 multi-stage noise-shaping (MASH) delta-sigma modulator (DSM) with a passive noiseshaping successive approximation register (NSSAR) ADC was proposed.
Abstract: This paper presents a hybrid CT/DT0-2 multi-stage noise-shaping (MASH) delta-sigma modulator (DSM) with a passive noise-shaping successive approximation register (NSSAR) ADC as the $2^{\mathrm{n}\mathrm{d}}$ stage. The overall architecture is simple and robust. The front-end stage employs the continuous-time (CT) operation to perform coarse quantization and provide inherent anti-aliasing and easy driving. The back-end stage uses a second-order NS-SAR architecture, which excels at PVT robustness, power efficiency, and scaling friendliness. It also results in large relaxation of matching issues between the analog and the digital domains compared with conventional CT-MASH. Behavioral simulation results demonstrate the effectiveness and robustness of the proposed hybrid MASH architecture.
Journal ArticleDOI
TL;DR: In this article , a BJT-based CMOS temperature sensor with a wide sensing range from −50 °C to 180 °C is presented, which introduces a nonlinear subranging readout scheme together with double sampling to achieve dynamic reconfiguration of the sensor readout according to the ambient temperature.
Abstract: This article presents a BJT-based CMOS temperature sensor with a wide sensing range from −50 °C to 180 °C. To effectively relax the sensor resolution requirement and conversion time over the entire temperature range to improve energy efficiency, we introduce a nonlinear subranging readout scheme together with double sampling to achieve dynamic reconfiguration of the sensor readout according to the ambient temperature. We further reduce the sensor power at high temperature by devoting the $\beta $ -cancellation circuit only for BJT biasing while applying a temperature-independent bias current for the other sensor building blocks. Implemented in 0.18- $\mu \text{m}$ CMOS with four-wire connections and switch-leakage compensation based on small BJTs, the proposed sensor chip prototype achieves a high resolution-FoM of 7.2 pJ $\cdot \text{K}^{{2}}$ at 150 °C, while featuring a small sensing error of ±0.45 °C under a 1.5-V supply.
References
More filters
Journal ArticleDOI
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

399 citations

Journal ArticleDOI
James C. Candy1
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.

342 citations

Journal ArticleDOI
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

284 citations

Book ChapterDOI
James C. Candy1, O. Benjamin1
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.

255 citations

Journal ArticleDOI
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >

211 citations