Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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01 Nov 2015
TL;DR: This paper presents an all-digital time-mode first-order ΔΣ ADC with 3-bit gated VCO quantizer, which consists of a voltage- to-time integrator that performs both voltage-to-time conversion and feedback subtraction, a 7-stage gated current-starved ring oscillator as a3-bit quantizer and a digital differentiator that provides both first- order noise-shaping and frequency feedback.
Abstract: This paper presents an all-digital time-mode first-order ΔΣ ADC with 3-bit gated VCO quantizer. The ΔΣ ADC consists of a voltage-to-time integrator that performs both voltage-to-time conversion and feedback subtraction, a 7-stage gated current-starved ring oscillator as a 3-bit quantizer, and a digital differentiator that provides both first-order noise-shaping and frequency feedback. Implemented in IBM 0.13 μm 1.2V CMOS technology, the ADC provides SNDR of 47.4 dB and SFDR of 34.1 dB over 4 MHz bandwidth. The power consumption of the ADC is 1.1mW. The silicon consumption excluding bonding pads of the ADC is 470 × 470 μm2.
TL;DR: In this paper, the authors introduce a time-interleaved architecture to tackle the speed-resolution bottleneck of the noise-shaping (NS) successive approximation register quantizer in a continuous-time (CT) sigma-delta modulator (SDM).
Abstract: This work introduces a time-interleaved architecture to tackle the speed-resolution bottleneck of the noise-shaping (NS) successive approximation register (SAR) quantizer in a continuous-time (CT) sigma-delta modulator (SDM). A critical insight is that introducing a delay in the NS quantizer feedback loop enables complete parallelization of the NS quantizer operations. The extra time from parallelization greatly relaxes loop filtering and residue integration and enables a high quantizer resolution. Furthermore, the extra time in the feedback loop allows data weighted averaging (DWA), which eliminates the need for calibration. The prototype comprises a second-order CT front-end and a fully interleaved first-order NS quantizer. The prototype is fabricated in a 28 nm process, occupies 0.072 mm2 and consumes 6.4 mW. The peak signal-to-noise ratio (SNR), signal-to-noise-distortion ratio (SNDR), and dynamic range (DR) are 83.9, 81.6, and 84.8 dB, respectively, in a 15.625 MHz bandwidth. The corresponding Schreier SNDR figure of merit (FoM) is 175.5 dB.
DOI•
TL;DR: In this paper , the authors present a system-on-a-chip (SoC) for pressure sensors in 180-nm CMOS technology, which can interface with a capacitive pressure sensor with an inductive wireless power supply and data transmission via load-shift keying.
Abstract: This article presents a system-on-a-chip (SoC) for pressure sensors in 180-nm CMOS technology. It can interface with a capacitive pressure sensor with an inductive wireless power supply and data transmission via load-shift keying (LSK). It integrates an analog front end (AFE), bandgap references (BGRs), delta-sigma ADC, I2C, RC oscillator, low-dropout regulators (LDOs), shorting control switches, and full-bridge rectifier (Rct). An external coil receives wireless power, which is rectified and regulated to 1.8 V by the full-bridge Rct and LDOs. The AFE samples the capacitance change of the pressure sensor to a voltage that is converted into 19-bit digital data by the delta-sigma ADC, which is then converted into 43 Hz per sample serial data by the I2C block. A temperature sensor is included, and 19-bit measurements are transmitted in serial with capacitance data. Serial data are transmitted wirelessly using LSK. This SoC has a measured accuracy of 1 mmHg between 575- and 900-mmHg absolute with a wireless power supply and wireless data transfer.
Dissertation•
01 Jan 2018
01 Jan 2010
TL;DR: Substantial differences in the ways that usage guides treated usage problems and in the attitudes bloggers and journalists espoused towards the usage problems are revealed.
Abstract: .......................................................................................................................... xvi CHAPTER
References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations