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Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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TL;DR: In this paper , a third-order cascade of integrators with feed-forward (CIFF) delta-sigma analog-to-digital converter (ΔΣ-ADC) was designed for MEMS gyroscope fully differential sensing.
01 Jan 2016
TL;DR: This thesis presents detailed design of the critical analog circuit blocks of the pipeline ADC, covering two fabricated 130-nm 440MS/s programmable 5-8-bit ADC prototypes for a SAR receiver, and the design and measurement results of a 200-400-mV 5.8-Gbps 40-nm CMOS voltage-mode transmitter driver consuming inherently low power.
Abstract: Nowadays, a high-speed medium-accuracy analog-to-digital converter (ADC) is required in numerous applications, such as a synthetic aperture radar (SAR) system, wireless local area network (WLAN) receiver, or DVD and Blu-Ray readout. As one of the two main parts, this dissertation presents the design and implementation of wideband high-speed medium-accuracy pipeline ADC as a part of a receiver of a SAR system, implemented in a deep-submicron CMOS process. Technology scaling of modern narrow line width CMOS processes has enabled higher bandwidths, but from dynamic range and accuracy perspectives, analog design of integrated circuits has become more challenging. This thesis presents detailed design of the critical analog circuit blocks of the pipeline ADC, covering two fabricated 130-nm 440-MS/s programmable 5-8-bit ADC prototypes for a SAR receiver. Due to their flexibility, the ADCs can be optimized for several standards in accordance with the accuracy and power. The second ADC was also measured together with the entire receiver.
The ADC discussion of this thesis is twofold, and the SAR receiver discussion is followed by a design case of an ADC for pressure sensors, where low power and high accuracy are required.The design and measurements of a 350-nm 28-microwatt 14-bit 16-kS/s Delta Sigma modulator are presented. Adequate accuracy and low consumption of total system power make the modulator a very suitable structure for this indicated application.
The other main part of this thesis consists of high-speed IO drivers in modern wideband transceivers. Nowadays, multi-functional mobile phones need to be of a compact size, and thus serial link wireline IO drivers are tempting alternatives to be used for the internal communication. This leads to very rapid data rates and a challenging EMI environment in proximity to the IO, and the coupling of EMI to radio receivers inside the same device becomes critical. Furthermore, in a battery-powered system the power consumption should be minimized. Conventional current-mode drivers can achieve very low output noise, at a cost of several times higher power consumption compared to voltage-mode drivers. This thesis presents the design and measurement results of a 200-400-mV 5.8-Gbps 40-nm CMOS voltage-mode transmitter driver consuming inherently low power. As an original research work, the measurements show sufficiently low output noise, making the driver a suitable structure to be used in mobile devices. The high-speed IO driver discussion is completed with design examples of an 8-Gbps LVDS input data interface and an 8-GHz local oscillator signal buffer and divider for a LTE base station transmitter. ; Nopea ja kohtuullisen tarkka A/D-muunnin on oleellinen piirilohko lukuisissa nykyaikaisissa sovelluksissa. Toisena paakokonaisuutena tama vaitoskirja tarkastelee liukuhihna-A/D-muuntimen suunnittelua osana kapean viivanleveyden CMOS-teknologialla integroitua laajakaistaista synteettisen apertuuritutkan vastaanotinta. Nykyaikaiset CMOS-teknologiat ovat mahdollistaneet aiempaa…
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...A higher order modulator with improved stability can be implemented by utilizing a multi-stage noise shaping (MASH) architecture [13, 14, 109], which cascades lower order modulators, for example a second and a first order one to obtain third order noise shaping....
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...In general, ∆Σ loops higher than second order can potentially be unstable [13, 14, 109], and utilizing a second order loop is advantageous in that point of view....
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...The contributions of the second integrator and the quantizer are assumed to be negligibly small, because they are attenuated by a first and second order high-pass NTF, and because the OSR is large [109]....
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...Linear analysis shows degradation of the NTF through a finite integrator gain at DC, suggesting that the quantization noise attenuation provided by a second order loop does not degrade significantly if A0 ≥ OSR·Cs1 π·Ci1 [109], which in this case is around 12....
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...In general, for an Lth order ∆Σ noise shaping loop the inband quantization noise power is approximately [109]...
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30 Sep 2013
TL;DR: In this paper, a couple of first-order and second-order frequency discriminator structures are modeled and analyzed with their quantization noise sources and a delta-sigma frequency detector architecture is proposed.
Abstract: Frequency detector is a circuit that converts the frequency to a digital representation and finds its application in various fields such as modulator and synchronization circuitry. In this paper, a couple of first-order and second-order frequency discriminator structures are modeled and analyzed with their quantization noise sources. Also a delta-sigma frequency detector architecture is proposed. Through theoretical analysis and derived equations, the output noise is obtained, which is validated by simulation. The proposed all-digital frequency discriminator may be applied in the feedback path of the all-digital phase-locked loop.
Additional excerpts
...델타-시그마 변조기[4]처럼 잡음을 고대역 통과 필터링(high-pass filtering)시켜주는, 즉 noise shaping시켜주는 주파수 판별기를 델타-시그마 주파수 판별기라고 부른다....
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...한편, 그림 2(b)의 MASH 2차 구조는 그림 5(b)의 2차 디지털 변조기[4]와 유사하게 동작한다....
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...누적기의 전달함수 Hacc(z)=z /(1-z)=1/(z-1)과 같 이 놓을 수 있으므로[4] (단, 지연형, 즉 delayed type 일 경우), 그림 4로부터 다음의 (2)를 얻는다....
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...1차 델타-시그마 주파수 판별기는 원하는 신호 대역 내의 잡음이 평평한 반면에, 2차 델타-시그마 주파수 판별기는 신호 대역 내에서 잡음이 감소하도록 noise shaping 된다[4]....
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...델타-시그마 변조 기 차수가 l일 때 주파수 변조기의 양자화 잡음의 전 력밀도는 (1)과 같다[4]....
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References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations