Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
More filters
01 Jul 2007
TL;DR: The 3rd-order reconfigurable serial single stage sigma-delta modulator using a new design methodology is proposed and verified and will be used in frequency synthesizer for low noise characteristics supporting other frequencies.
Abstract: Frequency synthesizer has been developed to support various communication systems in recent wireless communication systems. Consequently, the design of frequency synthesizer which is suitable for high performance communication system is essential, and frequentcy synthesizer must maintain low phase noise. The design of VCO and fractional divider is important in frequency synthesizer which is based on PLL. Specially, sigma-delta modulator is one of important design blocks when fractional frequency synthesizer is integrated in low noise system. But, the design methodology which is accurate for sigma-delta modulator in fractional frequency synthesizer is not shown in most designs. Also, the needs of reconfigurable sigma-delta modulator for low noise characteristics supporting other frequencies is increasing nowadays. In this paper, the 3rd-order reconfigurable serial single stage sigma-delta modulator using a new design methodology is proposed and verified.
14 Nov 2016
DOI•
01 Jan 2014
TL;DR: In this paper, an Analog-to-Digital Converter and Sigma-Delta Modulation (SDM) were used to achieve ultra-high resolution and high-level simulation.
Abstract: Keywords: Analog-to-Digital Converter ; Sigma-Delta Modulation ; Switched-Capacitors ; Ultra-high resolution ; Modeling ; High-level Simulator ; Incremental Converter ; Optimal Filter ; System-on-Chip These Ecole polytechnique federale de Lausanne EPFL, n° 6174 (2014)Programme doctoral Microsystemes et MicroelectroniqueFaculte des sciences et techniques de l'ingenieurInstitut de genie electrique et electroniqueLaboratoire d'electronique generale 1Jury: Dr J.-M. Sallese (president) ; Prof. M. Kayal, Dr F. Krummenacher (directeurs) ; Dr Ph. Deval, Prof. F. Maloberti, Dr A. Schmid (rapporteurs) Public defense: 2014-6-27 Reference doi:10.5075/epfl-thesis-6174Print copy in library catalog Record created on 2014-06-12, modified on 2016-08-09
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...This block representation is used in many high-level simulators, the best known are the ’Delta Sigma Toolbox’ [42], ’SIMSIDES’, [43], ’Daisy’ [44] and the ’SD Toolbox’ [45]....
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...The second figure of merit, mainly used to compare high-resolution converters is: FOM2 = P 22E NOB fs (1.2) Obviously, the best way to agree with both definitions would be to compare only converters with identical resolutions....
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...The first one is: FOM1 = P 2E NOB fs (1.1) Historically the oldest one, it is not suited for converters in which the thermal noise dominates (i.e....
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...The most popular are probably Richard Schreier’s toolbox [42, 55] and SIMSIDES [43, 56], a simulator developed in a Matlab Simulink environment by José M....
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...2) One of the most commonly used Figure Of Merit to compare high-resolution converters is derived from Schreier’s FOM [42]....
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DOI•
TL;DR: In this paper , an fA-level-sensitivity and 115-dB-DR current domain (CD) continuous-time (CT) Zoom ADC-based CSFE is presented, which achieves the power efficiency of 389 nJ per conversion and a resolution Figure-of-Merit (FoM) of 0.13 pA.
Abstract: Ultrahigh sensitivity and large-dynamic-range (DR) current-sensing front-ends (CSFEs) are required in emerging biomedical applications like next-generation gene-sequencers (NGGSs). In this article, an fA-level-sensitivity and 115-dB-DR current-domain (CD) continuous-time (CT) Zoom ADC-based CSFE is presented. Three main techniques are proposed, including: 1) a novel resistive-DAC (RDAC) with ultralow noise and a compact area to achieve an fA-level sensitivity; 2) a CD CT SAR ADC serves as a coarse quantizer to extend the DR to be over 115 dB; and 3) a digital compensation scheme overcomes the offset problem of the big parasitic capacitor at the input node. Fabricated in a 180-nm CMOS process, this chip only occupies an active area of 0.182 mm2 and consumes $77 \mu \text{W}$ at a 2-V supply voltage. At a 100-Hz bandwidth (BW), it achieves the power efficiency of 389 nJ per conversion and a resolution Figure-of-Merit (FoM $_{\text {res}}$ ) of 0.13 pA $^{{2}}\mu \text{J}$ .
01 Nov 2020
TL;DR: A 2+2 switched-current (SI) multi-stage noise-shaping (MASH) delta-sigma modulator (DSM) with a digital noise-cancellation circuit (DNCC) with advantages of its small chip area and high processing speed at all input currents is proposed.
Abstract: This paper proposes a 2+2 switched-current (SI) multi-stage noise-shaping (MASH) delta-sigma modulator (DSM) with a digital noise-cancellation circuit (DNCC) by using a TSMC 0.18 μm 1P6M CMOS process. In view of area-efficiency, the current-mode sample-and-hold circuit (S/H) is designed to reduce the chip area considerably. It plays a vital role in the performance of the DSM. Note that the input impedance of the modified current-mode feedback memory cell (FMC) is decreased by [2 + (g'm3/gml-1) x A] times relative to a traditional FMC and the input current is being processed more quickly. However, it suffers the transmitted error particularly for small input currents. The MASH architecture inherited a superior signal-to-noise-and-distortion ratio (SNDR) by using an effective digital noise cancellation circuit (DNCC) and a low-pass filter varied from 10 Hz to 20 kHz. The designed current-mode DNCC is composed of six delay components using master-slave D flip-flop and a logic circuit using the karnaugh map. Post-layout simulations reveal that the simulated SNDR was 90.4 dB and the ENOB was 14.73 bits. The designed IC consumes 18.19 mW at a chip area of 0.13 mm2 and a simulated FoM of 24.5 pJ/conv. The advantages of our modulator are its small chip area and high processing speed at all input currents.
References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations