Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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07 Aug 2022
TL;DR: In this article , the authors presented several enhancements to the sturdy multi-stage noise-shaping delta-sigma modulators, which improved the resolution and allowed faster conversion speed without losing the dynamic range by employing noisecoupling and multi-bit quantizer at the second stage.
Abstract: This paper presents several enhancements to the sturdy multi-stage noise-shaping delta-sigma modulators. The proposed topology improves the resolution and allows faster conversion speed without losing the dynamic range by employing noise-coupling and multi-bit quantizer at the second stage. Furthermore, a unity signal transfer function loop architecture presented in previous work is included to cancel the quantization noise of the first loop and improve the overall dynamic range. Simulation results demonstrate the effectiveness of the proposed delta-sigma modulator and its suitability for high-resolution sensor systems. Up to 30 dB Signal-to-quantization noise ratio (SQNR) improvement and more than 20 dB SQNR with 1% deviation is achieved with the proposed architecture without compromising from the maximum stable amplitude.
TL;DR: A low-pass interpolation filter with adjustable oversampling ratio applied in a 24-bit audio DAC with verified by FPGA and synthesized by DC tools that can meet the audio specifications.
Abstract: Interpolation Filter plays an important part in the Sigma-Delta DAC. This paper describes a low-pass interpolation filter with adjustable oversampling ratio applied in a 24-bit audio DAC. The interpolation filter we design is a 3-stage structure with two stages half-band pass filter and a novel high ratio interpolation filter. We apply a novel structure of hardware to implement the half-band pass filter. Compare with traditional method, the new method only costs four group adders and the same size ROM and RAM to complete the work. The third stage of the interpolation filter we design to implement high ratio interpolation. We just use normal logic and time units to replace the CIC (Cascaded Integrator-Comb) filer without any adders applied. The in-band SNR and THD can achieve about 131.9 dB and - 90.5 dB in the actual work situation. We design it aided by the Matlab&Simulink. The filter has been verified by FPGA and synthesized by DC tools. The performance of the filter can meet the audio specifications.
Additional excerpts
...5 { [( (1) ( 1) ) ( (3) ( 1) ) ( ( 1) ( 1) )]} 2 2 0....
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...( /2) 2 ( ) [ (1)(1 ) (3)( ) ( 1)( )] 2 N N...
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...( /2) ( ) [( (1) ( 1) ) ( (3) ( 1) ) ( ( 1) ( 1) )] 2 2 ( ) 2 N N...
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...' ( /2) 1 ( /2) 1 0 [ (1)(1 ) (3)( ) ( 1)( )] 2 N N...
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TL;DR: By using a clock and data recovery circuit at the receiver to reduce jitters, the single-sideband phase noise of the generated signals can be significantly reduced.
Abstract: We propose a delta-sigma modulation scheme for low- and medium-frequency signal transmission in a digital photonic network system. A 10-Gb/s-class optical transceiver with a delta-sigma modulator utilized as a high-speed analog-to-digital converter (ADC) provides a binary optical signal. On the signal reception side, a low-cost and slow-speed photonic receiver directly converts the binary signal into an analog signal at frequencies from several hundreds of kilohertz several tens of megahertz. Further, by using a clock and data recovery circuit at the receiver to reduce jitters, the single-sideband phase noise of the generated signals can be significantly reduced.
Cites background from "Understanding Delta-Sigma Data Conv..."
...In general, the signal-to-quantized-noise ratio (SQNR) is given by 20 log(2N − 1), where N denotes bit resolution, for example, 72 dB for a 12-bit ADC.10 Therefore, to achieve a dynamic range greater than 70 dB, the bit resolution of the ADC should be greater than 12 bits....
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...PRINCIPLE OF DELTA-SIGMA MODULATION A ∆Σ modulator is a kind of ADC.(9) In conventional ADCs, especially in a Nyquist-sampling ADC, bit resolution is one of the most important factors for evaluating signal quality....
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...A ∆Σ modulator is a kind of ADC.9 In conventional ADCs, especially in a Nyquist-sampling ADC, bit resolution is one of the most important factors for evaluating signal quality....
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04 Dec 2007
TL;DR: Simulation results show that this novel 2-3 two-stage fifth-order multi-bit cascade sigma-delta modulator architecture is insensitive to the nonlinear and finite gain of op-amp.
Abstract: In this paper, a novel 2-3 two-stage fifth-order multi-bit cascade sigma-delta modulator (SDM) architecture is proposed for broadband applications For low oversampling applications, in order to resolve the problem of the sensitivity to the nonlinear and finite gain of operational amplifier (op-amp) in the traditional cascade SDM architecture, the first stage of the proposed SDM architecture employs a second-order low-distortion multi-bit SDM While the second stage employs a single-loop third-order multi-bit SDM instead of a first-order or second-order SDM, which can simplify the analog circuit significantly The noise transfer function and the interstage gain between the first stage and second stage are carefully designed for stability considerations Furthermore, the simplified digital cancellation logics can be achieved Simulation results show that this SDM architecture is insensitive to the nonlinear and finite gain of op-amp
01 Jan 2012
TL;DR: This chapter will present recent developments of MEMS feedback control from the perspectives of application, design method, and implementation.
Abstract: The miniaturization of actuators by microelectromechanical systems (MEMS) allows an increased mechanical bandwidth that can be utilized for improving response speed and control accuracy. MEMS also brings new control problems, such as control of electrostatic microactuators, to inspire both the MEMS and control communities to work together. This chapter will present recent developments of MEMS feedback control from the perspectives of application, design method, and implementation.
Cites methods from "Understanding Delta-Sigma Data Conv..."
...If one integrator (M = 1) and one-bit quantization are used, the in-band noise power is given by [69]...
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References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations