Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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01 Jan 2014
TL;DR: In this article, the authors discuss eddy-current displacement sensors (ECSs), one of the most widely used measurement techniques in harsh environments, and provide a review of state-of-the-art ECS interfaces.
Abstract: This chapter discusses eddy-current displacement sensors (ECSs) – one of the most widely-used measurement techniques in harsh environments. First, in Section 4.1, we briefly discuss ECS applications in industry. In Section 4.2, the operation principle, the limitations and important design considerations of this type of sensor are surveyed. The ECS performance limitations are addressed in Section 4.3, considering the most demanding industrial applications. Special attention is given to the excitation frequency, the design of the sensor and its electronic interface. Sections 4.4 and 4.5 provide a review of state-of-the-art ECS interfaces. The chapter ends with conclusions and design perspectives for ECS systems.
01 Aug 2018
TL;DR: A 3rd-order single-loop 1-bit discrete time (DT) ∑-Δ modulator is designed and implemented in a 40-nm CMOS process and a simple pure dynamic comparator is used to save power consumption.
Abstract: A 3rd-order single-loop 1-bit discrete time (DT) ∑-Δ modulator is designed and implemented in a 40-nm CMOS process. The single-loop 1-bit topology is selected because it is less sensitive to non-idealities of the devices and consumes less power. As a result of design optimization, the order is set to 3 and the oversampling ratio (OSR) is chosen to 128. The value of sampling capacitor is set to 2.6 pF to satisfy the noise requirements. In order to adapt low-voltage environment, the two-stage operational amplifier is implemented in the integrator instead of the cascode architecture. Since the design requirement for the comparator is not stringent in the modulator, a simple pure dynamic comparator is used to save power consumption. The simulated output spectrum show that the proposed modulator achieves a peak signal to noise ratio (SNR) of 87.9 dB in the signal bandwidth of 100 kHz with the sampling frequency of 25 MHz. The total power consumption is 2.1 mW under a 1.2-V supply.
Cites background from "Understanding Delta-Sigma Data Conv..."
...ARCHITECTURE OF THE Σ-Δ MODULATOR There are several choices in deciding the architecture of a Σ-Δ modulator [7, 8]....
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03 Sep 2008
TL;DR: The proposed configuration increases modulator throughput by decomposing a delta-sigma loop into two events, which can be completed in one input clock period, and an output/input rate ratio of 1:1 is obtained.
Abstract: In this paper, we propose an implementation for digital delta-sigma modulators named as threshold direct synthesis structure. The proposed configuration increases modulator throughput by decomposing a delta-sigma loop into two events, which can be completed in one input clock period. A third-order single-loop digital modulator is implemented using this method and an output/input rate ratio of 1:1 is obtained. Since a relatively low circuit speed is allowed, it can be used for a low power fractional-N frequency synthesizer implementation.
01 Jul 2017
TL;DR: A dual-mode low pass sigma-delta modulator at clock rates respectively with cascaded integrators is presented for wireless sensor and communication applications and has built in near-infrared laser-driven (NIRLD) might be a promising wireless electrical power source.
Abstract: A dual-mode low pass sigma-delta (ΣΔ) modulator at clock rates respectively with cascaded integrators is presented for wireless sensor and communication applications. One of key features is that cascaded integrators with feedback as well as distributed input coupling (CIFB) topology erase a summation amplifier and reduce consumption by wake up receiver. In near feature is that only one set loop filter is designed by switching capacitors to achieve a dual-mode function and greatly optimized layout placement. The multi-charging proposal has built in near-infrared laser-driven (NIRLD) might be a promising wireless electrical power source. The proposed breathing analog to digital converter of modulator senses CO 2 concentration detecting instruments on chipset. Oxygen generator will fast to support when sensor monitor and wireless send bio-signal to health cloud and big data.
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...The cascaded integrators with distributed feedback as well as distributed input coupling (CIFB) and the loop filter with distributed feedforward and input coupling (CIFF) are commonly used in modulators [1]....
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...Literature [1] proposed a fifth-order modulator with hybrid active-passive loop filters....
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16 May 2011
TL;DR: In this article, a third-order Sigma-#Delta modulator with the design-for-digital-testability (DfDT) structure was proposed for audio applications.
Abstract: This paper presents the design of a third-order Sigma-#Delta modulator with the design-for-digital-testability (DfDT) structure for audio applications. The DfDT structure not only makes the Sigma-#Delta modulator digitally testable but also provides many test benefits such as a low hardware overhead, high fault observability, high test accuracy, and the capability of conducting at-speed tests. The zero in the noise transfer function of the proposed third-order Sigma-#Delta modulator vanishes the shaped quantization noises near the passband. As a result, the shaped noise correction of the digital tests is less significant. It helps improve the test accuracy of the digital tests. The simulation results with the fully-settled linear behavior plus noise (FSLB+N) model show that the peak SNDR and the dynamic range of the proposed third-order Sigma-#Delta modulator using conventional analog stimuli are 86.8 dB and 90.6 dB respectively at an over-sampling ratio (OSR) of 64. The SNDR differences between analog tests and those of the corresponding digital tests are in-between 0.9 dB and -1.4 dB with an average of 0.06 dB when the Sigma-#Delta modulator is not overloaded. In addition, both kinds of tests have similar effective resolution bandwidth results (ERBW). The simulation results confirm that the proposed Sigma-#Delta modulator can have a low test cost and thus is suitable for SoC and built-in self-test (BIST) integrations thanks to the DfDT structure.
Cites methods from "Understanding Delta-Sigma Data Conv..."
...SIMULATION RESULTS Due to the over-sampling and the nonlinear nature of Σ-Δ modulators, the simulation time is too long by using circuitlevel simulation tools like HSPICE [2], [16]....
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References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations