Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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01 Oct 2014
TL;DR: A novel speculative pseudo-Parallel ΔΣ modulator structure is presented, which almost halves the logic depth of the critical path in the pseudo-parallel Hatami structure, and circumvent the block-to-block dependence of theHatami structure.
Abstract: We present a novel speculative pseudo-parallel ΔΣ modulator structure, which almost halves the logic depth of the critical path in the pseudo-parallel Hatami structure. Following Hatami, our modulator calculates a block of n consecutive output bits in parallel, and then employs a parallel-serial interface to output the bits at n times the modulator clock frequency. We circumvent the block-to-block dependence, which limits the clock speed of the Hatami structure, by speculatively calculating the outputs based on all possible output values of the previous block, and then selecting the correct one. We present cost and performance estimates for an initial implementation of the modulator, synthesized towards an FPGA and an ASIC technology.
Cites background from "Understanding Delta-Sigma Data Conv..."
...In particular, a core quantizer resolution of only one bit eliminates many linearity concerns [1]....
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01 Jan 2011
TL;DR: This thesis presents a type of delta sigma modulator which focuses on using of low gain operational amplifier and hence to operate at low voltage technologies and be more power efficient.
Abstract: Data converters are one of the key components in many applications ranging from wireless communication to data acquisitions system, sensors, audio electronics, video display electronics and analog microcontrollers. All of these use some type of data converter to perform the task of signal processing/condition for example in RF transceivers the received analog signal after passing through filters is converted to digital signal for further processing. The use of delta-sigma modulators nowadays are gaining popularity over the other A/D converters because of sampling and noise shaping. Also the architecture of delta sigma modulator is a mixed system, and digital filters are present (to remove noise in case of MASH architecture) so because of these reason many programmable features can be used in the applications employing delta sigma modulator. This thesis presents a type of delta sigma modulator which focuses on using of low gain operational amplifier and hence to operate at low voltage technologies and be more power efficient. Two topologies were presented, one having a single loop architecture but with a very highly aggressive NTF and other using multi-stage architecture with no additional digital filter to achieve the required specifications. The thesis presents the complete system analysis of the topologies, and the non-idealities modeling at system level. Then the transistor level design of the designed topologies was done in Cadence in 90nm CMOS. Each component of the designed modulator was tested individually at circuit level. The complete system was analyzed using the Verilog-A model.
13 Mar 2017
TL;DR: This work presents a low cost automatic method to test vector generation for defect-oriented structural analog testing by computing the frequency response of circuit nodes, while iteratively injecting faults, using a SPICE simulator.
Abstract: This work presents a low cost automatic method to test vector generation for defect-oriented structural analog testing. An optimal set of analog single tone signals is obtained by computing the frequency response of circuit nodes, while iteratively injecting faults, using a SPICE simulator. The method also allows to identify the nodes of the circuit with higher observabilities to the injected faults, by comparing the obtained fault coverage as a function of frequency. A 130 nm ΣΔ modulator is used as case study to validate the technique under fault injection campaigns. Up to 100% fault coverage is obtained depending on the number of test points. A trade-off is identified, in such a way that a single test point may be used, achieving 95% of fault coverage. The optimized sets of single tone signals can be either combined in a multi-tone testing strategy or sequentially applied during the test application phase.
Cites methods from "Understanding Delta-Sigma Data Conv..."
...The circuit topology is a Cascade of Integrators FeedForward (CIFF) [9] and it was implemented with active-RC integrators and a current-steering non-return-to-zero (NRZ) DAC as shown in Fig....
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TL;DR: In this article, the authors introduce a family of second-order sigma delta quantization schemes for analog-to-digital conversion which are ''quiet'' : quantization output is guaranteed to fall to zero at the onset of vanishing input.
Abstract: In this paper, we introduce a family of second-order sigma delta quantization schemes for analog-to-digital conversion which are `quiet' : quantization output is guaranteed to fall to zero at the onset of vanishing input. In the process, we prove that the origin is a globally attractive fixed point for the related family of asymmetrically-damped piecewise affine maps. Our proof of convergence is twofold: first, we construct a trapping set using a Lyapunov-type argument; we then take advantage of the asymmetric structure of the maps under consideration to prove convergence to the origin from within this trapping set.
Cites methods from "Understanding Delta-Sigma Data Conv..."
...Although high-order Σ∆ quantizers have been implemented in practice for many years [15], the construction of Σ∆ schemes of arbitrary order m ≥ 1 for which the state sequence (vn)n∈N is guaranteed to remain bounded has been only recently achieved by Daubechies and DeVore in [4]: Proposition 1....
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Cites methods from "Understanding Delta-Sigma Data Conv..."
...Thus, it is suitable to realize the high resolution ADC in nanometer CMOS technology [8, 9]....
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References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations