Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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01 Jan 2012
TL;DR: In this article, the authors investigated the energy efficiency of multi-bit ΔΣ modulators in terms of a normalized power dissipation, which is commonly referred to as the figure-of-merit (FOM).
Abstract: Energy efficiency of multi-bit ΔΣ modulators has been investigated in terms of a normalized power dissipation, which is commonly referred to as the figure-of-merit (FOM). The multi-bit modulators are designed by adding a multi-level comparator and feedback path to a conventional inverter-based modulator. The FOM is estimated by transistor-level circuit simulation assuming a 0.18-μm standard CMOS technology. In the present 3-bit modulator, the FOM is improved by more than a factor of two compared with a conventional 1-bit one. By using the multi-level comparator, the smaller quantization error reduces the settling time in the integrators, and then improves the energy efficiency.
Cites background from "Understanding Delta-Sigma Data Conv..."
...This agrees well with a prediction made for ΔΣ modulator in general [1]....
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...In addition, requirements on the stability, linearity, and the slew rate can be alleviated by adopting the multi-bit scheme [1], [8–11], since the feedback signal is smaller in the multi-bit ΔΣ modulators than that in the conventional 1-bit ones....
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...Among others, ΔΣ ADCs, consisting of a ΔΣ modulator and a following digital filter for decimation, have drawn increasing attentions, recently, because they can provide higher resolution than any other architectures by utilizing oversampling and noiseshaping techniques [1]....
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01 May 2019
TL;DR: Several techniques, including chain of integrators with weighted feedforward structure, gain-enhanced current-mirror push-pull operational transconductance amplifier, and dynamic comparator with a set-reset latch are adopted to improve the signal-to-noise ratio (SNR) and reduce the power consumption.
Abstract: The study proposed a switched-capacitor delta-sigma modulator with single-loop and third-order structures for wearable electrocardiogram acquisition device for low-power and high-precision applications. Several techniques, including chain of integrators with weighted feedforward structure, gain-enhanced current-mirror push-pull operational transconductance amplifier, and dynamic comparator with a set-reset latch are adopted to improve the signal-to-noise ratio (SNR) and reduce the power consumption. Simulation results shows that the SNR and the corresponding effective number of bits are 104.2 dB and 17.02 bits, respectively, which fulfill the requirements of an presented system. The circuit will be fabricated by the SMIC using a 0.18 μm general purpose process in the near future.
01 Dec 2016
TL;DR: This paper presents a new integrated Lab-On-a-Chip (LOC) based on Differential electric-field sensitive Field-Effect Transistor (DeFET) sensor array that is used in Biomedical Analysis and shows that the sensitivity of the DeFET sensor is appreciably enhanced.
Abstract: This paper presents a new integrated Lab-On-a-Chip (LOC) based on Differential electric-field sensitive Field-Effect Transistor (DeFET) sensor array that is used in Biomedical Analysis. The proposed system introduces a 4 × 4 DeFET sensor array, analog multiplexer, readout circuit, and Analog to Digital Converter (ADC) that perform the sensing, actuating, and signal conditioning tasks. The proposed LOC is verified using circuit level simulation in the UMC 130 nm CMOS technology node. Simulation results show that the sensitivity of the DeFET sensor is appreciably enhanced. The proposed LOC consumes 2.2 mA from 1.2 V supply. Besides that, the equivalent circuit, and the theory of operation of the DeFET sensor are discussed.
Cites methods from "Understanding Delta-Sigma Data Conv..."
...Utilizing the toolbox in [11], the modulator’s order and Oversampling Ratio (OSR) are found to be 3 and 32, consecutively....
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TL;DR: This brief gives a detailed analysis of the NTF of I-SD ADCs and the impact of its properties on the resulting SQNR and introduces as an example a modified CoI filter that allows to improve the ADC’s performance.
Abstract: In this brief the performance of I-SD ADCs based on the spectral description is discussed. It is based on the modulator and the reconstruction filter and accounts for the applied reset. The definition of the overall noise transfer function (NTF) enables the analysis of the performance of I-SD ADCs in frequency domain and consequently makes it possible to explain the inherent behavior of this type of ADC including reconstruction filter and non-idealities. In the state of the art, the performance of an I-SD ADC is either obtained by simulations or predicted via time-domain considerations. However, these simulations can become time consuming and time-domain considerations neglect non-idealities, especially in the case of a CT modulator. Only recently, a general way to describe the NTF of DT and CT I-SD ADCs was introduced. This brief gives a detailed analysis of the NTF of I-SD ADCs and the impact of its properties on the resulting SQNR. It discusses the influence of common reconstruction filters and based on this analysis, it introduces as an example a modified CoI filter that allows to improve the ADC’s performance.
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...the signal power Pin and the quantizer step size [1]....
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...In order to give a first overview of an I-SD ADC, the working principle of a first order ADC is introduced in time domain as commonly described in literature [1], [3]....
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...For free-running SD ADCs, the optimization of the NTF zeros is usually employed [1]....
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...However, its averaging behavior excludes it from being used in applications where sampleto-sample conversion is required [1]....
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...For the free-running NTF, the optimized zeros not only introduce a notch but also elevate the frequency components close to DC [1]....
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01 Jan 2014
TL;DR: The design of a 12 bit dynamic element matching (DEM) DACs which eliminates pulse shape, timing, and amplitude errors arising from component mis- matches as sources of non-linear distortion in high resolution DACs is shown.
Abstract: This paper shows the design of a 12 bit dynamic element matching (DEM) DACs which eliminates pulse shape, timing, and amplitude errors arising from component mis- matches as sources of non-linear distortion in high resolution DACs. This has been proved through analytical and simulation results in 0.18 ��m standard CMOS process. A set of sufficient conditions of the DEM encoder that ensure this effect, and a specific segmented DEM encoder that satisfies the sufficient conditions are presented here. Unlike the most previously published fully randomized DEM encoders, the complexity of this design does not grow exponentially with the number of bits of DAC resolution. Part of this DEM DAC may be included in noise cancellation circuit in ΔΣ fractional-N PLL. Analytical results are demonstrated with simulation results. Additionally, this paper provides the explanation of noise cancellation in ΔΣ fractional-N PLL and power dissipation versus circuit complexity trade off.
References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations