Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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TL;DR: In this paper, a single-loop three-order switched-capacitor sigma-delta modulator (SDM) with a standard 0.18um CMOS technology is presented.
Abstract: This paper presents the design and implementation of a single-loop three-order switched-capacitor sigma-delta modulator(SDM) with a standard 0.18um CMOS technology. A current optimization technique is utilized in proposed design to reduce the power of operational transconductance amplifier(OTA).Using a chain of Integrators with weighted feed-forward summation(CIFF) structure and optimized single-stage class-A OTA with positive feed-back to minimize the power consumption. The SDM has been presented with an over-sampling ratio of 128,clock frequency 6.144MHz,24kHz band- width, and achieves a peak SNR of 100dB,103dB dynamic range. The whole circuits consume 2.87mW from a single 1.8V supply voltage.
14 Feb 2012
TL;DR: A selective calibration technique is proposed that is aimed at reducing the area occupancy of conventional linearization circuits, and a statistical element selection algorithm for linearizing DACs is proposed.
Abstract: DAC Linearization Techniques for Sigma-delta Modulators. (December 2011) Akshay Godbole, B.E., Birla Institute of Technology & Science, Pilani Co-Chairs of Advisory Committee: Dr. Jose Silva-Martinez Dr. Aydin I. Karsilayan Digital-to-Analog Converters (DAC) form the feedback element in sigma-delta modulators. Any non-linearity in the DAC directly degrades the linearity of the modulator at low and medium frequencies. Hence, there is a need for designing highly linear DACs when used in high performance sigma-delta modulators. In this work, the impact of current mismatch on the linearity performance (IM3 and SQNR) of a 4-bit current steering DAC is analyzed. A selective calibration technique is proposed that is aimed at reducing the area occupancy of conventional linearization circuits. A statistical element selection algorithm for linearizing DACs is proposed. Current sources within the required accuracy are selected from a large set of current sources available. As compared with existing calibration techniques, this technique achieves higher accuracy and is more robust to variations in process and temperature. In contrast to existing data weighted averaging techniques, this technique does not degrade SNR performance of the ADC. A 5 th order, 500 MS/s, 20 MHz sigmadelta modulator macro-model was used to test the linearity of the DAC.
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...First order modulators improve the SNR at the rate of 9 dB for every doubling of the sampling rate [3]....
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...39 Figure 20 All possible element selections using RDWA algorithm for a 2-bit DAC [3] ....
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...One of the main motivations for using sigma-delta modulators is that they provide inherent noise shaping [3]....
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01 Jul 2019
TL;DR: Noise-shaping dual-slope converters show an interesting property which can be exploited in MASH converters and this property is utilized in this paper by building an audio bandwidth 1-1 MASH using two switched-capacitor dual- slope converters.
Abstract: In Multi-stAge noise-SHaping (MASH) topologies a higher order of noise-shaping is achieved via converter cascading. The quantization error of the first stage is extracted, processed by another stage and ideally cancelled from a reconstructed output signal. However, often the quantization error must be derived by a separate Digital-to-Analog Converter (DAC). This requires additional hardware and design effort. Noise-shaping dual-slope converters show an interesting property which can be exploited in MASH converters. At certain time points an equivalent representation of the quantization error is available in the voltage domain which can be simply sampled by the cascaded stage. This property is utilized in this paper by building an audio bandwidth 1-1 MASH using two switched-capacitor dual-slope converters. Circuit level details including the timing diagram and MASH parameter estimation give adequate design insight. Digital and analog matching are the main disadvantage of MASH topologies. This quantization error leakage is discussed using system level mismatch analysis.1
Cites methods from "Understanding Delta-Sigma Data Conv..."
...The digital filters are implemented by satisfying the equation [6] H1 ·NTF1 −H2 · STF2 = 0....
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Dissertation•
01 Jan 2014
TL;DR: The speculative modulator structure, although it fails to achieve the tentative system specifications, exhibits a 46 % increase in operating frequency versus the regular Hatami structure, which has the potential for further investigation and design space exploration.
Abstract: As digital communication using MIMO antenna technology has emerged as a significant technological
breakthrough in modern communications, the need for reconfigurable experimental
MIMO systems has increased.
This project is a feasibility study of using !⌃ modulators for generating high-speed digital
signals on an FPGA chip synchronized to one local oscillator. The targeted performance specifications
are a 1 GHz carrier frequency, 100 MHz bandwidth, and 45 dB in-band SNDR. The
approach used to achieve the performance specifications is a novel speculative pseudo-parallel
!⌃ modulator based on the the method for unrolling a !⌃ modulator proposed by Hatami et
al.
The speculative modulator structure, although it fails to achieve the tentative system specifications,
exhibits a 46 % increase in operating frequency versus the regular Hatami structure. The
speculative modulator structure has the potential for further investigation and design space
exploration. The main reason for failing to reach the performance goal is suboptimal mapping
in the FPGA chip, which leads to relatively long routing delays with 69 % of the delay situated
in routing.
Cites background from "Understanding Delta-Sigma Data Conv..."
...In particular, a core quantizer resolution of only one bit eliminates many linearity concerns [1]....
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References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations