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Understanding Delta-Sigma Data Converters

TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
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Journal ArticleDOI
TL;DR: This paper presents a 0.5-V 12-bit low-voltage power-efficient successive-approximation register (SAR) analog-to-digital converter (ADC) using an adaptive time-domain (ATD) comparator with noise optimization using a differential threshold window technique.
Abstract: This paper presents a 05-V 12-bit low-voltage power-efficient successive-approximation register (SAR) analog-to-digital converter (ADC) using an adaptive time-domain (ATD) comparator with noise optimization To be power efficient with different residual input levels ( $\Delta V_{\mathrm {in}}$ ) during conversion, the proposed ATD comparator automatically adjusts its input-referred noise performance rather than consuming the same power for each bit conversion Considering the noise requirement of 12-bit resolution, the proposed ATD technique effectively reduces the comparator power consumption by 50% compared to the conventional approach Moreover, a differential threshold window (DTW) technique is also developed to provide the optimized time-domain threshold for lowest figure-of-merit (FoM) performance with a self-adjusted ( $V_{\mathrm {ctrlp}}$ – $V_{\mathrm {ctrln}}$ ), depending on process–voltage–temperature (PVT) variation The test chip occupies a core area of 0109 mm2 in Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm CMOS technology With a 05-V supply voltage, the prototype consumes 810 and 1425 nW at 100 and 250 kS/s, respectively The achieved effective number of bits and signal-to-noise and distortion ratio with Nyquist-rate input are 1071/103 bit and 663/638 dB, respectively The resultant Walden FoM and Schreier FoM are 482/452 fJ/conversion step and 1742/17323 dB, respectively

29 citations

Journal ArticleDOI
TL;DR: A mixed active-passive implementation of DeltaSigma modulators using a single active stage and two switched capacitor passive stages has performance advantages over traditional switched-capacitor (SC) or continuous-time implementations, particularly for high-resolution, wideband applications with high sampling rates and moderate oversampling ratios.
Abstract: We present a wideband architecture for DeltaSigma modulators using a single active stage and two switched capacitor passive stages. The mixed active-passive implementation has performance advantages over traditional switched-capacitor (SC) or continuous-time implementations, particularly for high-resolution, wideband applications with high sampling rates and moderate oversampling ratios. Design insensitivity to clock jitter and process variations is achieved by the good choice of the modulator architecture. The proposed modulator is designed in 0.13-mum CMOS technology and meets all major requirements for application in IEEE 802.16 wireless MAN receivers. Circuit simulations show that the modulator with a single bit quantizer consumes 5.5 mW from a 1.2-V power supply and achieves a 9-bit resolution over a 10-MHz bandwidth at an OSR of 32. Good performance is also achieved for lower bandwidth applications.

28 citations


Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...It is a single-loop third-order cascade-of-integrators, feedback form (CIFB), lowpass modulator [5] with a single bit quantizer....

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Journal ArticleDOI
01 Sep 2010
TL;DR: In this paper, a low-voltage 4-order 2-2 cascade delta-sigma (ΔΣ) modulator using the proposed double-sampling switched-operational-amplifier (SOP)-based integrator is presented.
Abstract: In this paper, a low-voltage fourth-order 2-2 cascade delta-sigma (ΔΣ) modulator using the proposed double-sampling switched-operational-amplifier (SOP)-based integrator is presented. In the analog part of the ΔΣ modulator, most of the power consumption comes from the SOP used in the integrator. Hence, the requirement of the SOP must effectively be relaxed to reduce the power consumption of the modulator. In each cascade stage, the second-order ΔΣ modulator with a cascade-of-integrators input feedforward structure is used to reduce the output swing. The second integrator output of the first stage is directly connected to the second stage to simplify circuit design on the analog part. Furthermore, the double-sampling SOP-based integrator is also adopted to reduce the applied clock frequency by half. In this paper, systematic means of designing the presented modulator and searching the minimum current of the SOP in a specified supply voltage are also developed. The presented ΔΣ modulator is fabricated in a 0.18- μm 1P6M CMOS technology. The chip core area without PADs is 1.57 mm2 . The modulator achieves an 84-dB peak signal-to-noise plus distortion ratio and an 88-dB dynamic range in 20-kHz signal bandwidth with a clock frequency of 2 MHz. The power consumption of the presented modulator core is 0.66 mW at a supply voltage of 1 V. The presented modulator can also be operated in a wide range of supply voltages from 1.8 V down to 0.9 V without seriously degrading the performance.

28 citations


Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...The odd-order harmonic tones, which are caused by the single-bit quantization [21], are apparent at the output of the first stage....

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  • ...The second-order integration function is chosen for loop filters to ensure the stability of the modulator [21]....

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Journal ArticleDOI
TL;DR: A formal computational model for algorithmic encoders and a general test bed for evaluating their robustness is proposed, based on a robust implementation of a beta-encoder with β = φ = (1 + √5)/2, the golden ratio.
Abstract: This paper proposes a novel Nyquist-rate analog-to-digital (A/D) conversion algorithm which achieves exponential accuracy in the bit-rate despite using imperfect components The proposed algorithm is based on a robust implementation of a beta-encoder with β = φ = (1 + √5)/2, the golden ratio It was previously shown that beta-encoders can be implemented in such a way that their exponential accuracy is robust against threshold offsets in the quantizer element This paper extends this result by allowing for imperfect analog multipliers with imprecise gain values as well Furthermore, a formal computational model for algorithmic encoders and a general test bed for evaluating their robustness is proposed

28 citations

01 Jan 2011
TL;DR: In this paper, a low-voltage low-power fourth-order single-bit continuous-time Delta-Sigma modulator is presented for audio applications, which employs an input-feedforward topology in order to reduce internal signal swings, thus relaxes the linearity and slew rate requirements on amplifiers leading to lowvoltage operation and low power consumption.
Abstract: The design of a low-voltage low-power fourth-order single-bit continuous-time Delta-Sigma modulator is presented in this paper for audio applications. The modulator employs an input-feedforward topology in order to reduce internal signal swings, thus relaxes the linearity and slew rate requirements on amplifiers leading to low-voltage operation and low-power consumption. The energy efficiency is further improved by em- bedding the summation of feedforward paths into the quantizer. For low-voltage operation, a gain-enhanced fully-differential amplifier and a body-driven rail-to-rail input CMFB circuit are developed. The modulator, implemented in a 0.13- ms tandard CMOS technology with ac ore area of 0.11 mm ,a chieves an 82-dB dynamic range (DR), and a 79.1-dB peak signal-to-noise and distortion ratio (SNDR) over a 20-kHz signal bandwidth. The power consumption of the modulator is 28.6 W under a 0.6-V supply voltage. The achieved performance make it one of the best among state-of-the-art sub-1-V modulators in terms of two widely used figures of merit.

28 citations

References
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Journal ArticleDOI
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

399 citations

Journal ArticleDOI
James C. Candy1
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.

342 citations

Journal ArticleDOI
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

284 citations

Book ChapterDOI
James C. Candy1, O. Benjamin1
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.

255 citations

Journal ArticleDOI
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >

211 citations