Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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TL;DR: In this paper, the authors propose a framework for optimal design based on the Kalman-Yakubovich-Popov (KYP) lemma and semi-definite programming.
Abstract: The Noise Transfer Function (NTF) of ΔΣ modulators is typically designed after the features of the input signal. We suggest that in many applications, and notably those involving D/D and D/A conversion or actuation, the NTF should instead be shaped after the properties of the output/reconstruction filter. To this aim, we propose a framework for optimal design based on the Kalman-Yakubovich-Popov (KYP) lemma and semi-definite programming. Some examples illustrate how in practical cases the proposed strategy can outperform more standard approaches.
23 citations
TL;DR: The proposed digital modulator dissipates the lowest power dissipation of all modulators compared, and by means of a proposed figure of merit, the proposed modulator exhibits very competitive performance.
Abstract: We present a micropower digital modulator for class-D amplifiers for power-critical digital hearing aids. The modulator design embodies a proposed Lagrange interpolation (a combined first- and second-order Lagrange) algorithmic pulsewidth modulation (PWM) and a third-order DeltaSigma noise shaper. By means of double-Fourier-series analysis, we analyze and determine the harmonic nonlinearities of the proposed algorithmic PWM. At 48-kHz sampling, 96-kHz PWM output, 997-Hz input, and input modulation index=0.9, the modulator circuit achieves a total harmonic distortion+noise n(THD+N) of - 74ndB (0.02%) over an 8-kHz voice bandwidth-a 12-dB THD+N improvement over a reported design and yet dissipates only ~ 50% of the power. The proposed modulator dissipates the lowest power dissipation of all modulators compared, and by means of a proposed figure of merit, the proposed modulator exhibits very competitive performance. The modulator IC is fabricated in a 0.35-mum digital CMOS process with a core area of 0.46 mm2.
23 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...The noise shaper is implemented using the error feedback structure [18], [20] whose -domain linear model is shown in Fig....
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01 Jan 2008
TL;DR: A wideband architecture for modula- tors using a single active stage and two switched capacitor passive stages has performance advantages over traditional switched-capacitor (SC) or contin- uous-time implementations, particularly for high-resolution, wideband applications with high sampling rates and moderate oversampling ratios.
Abstract: We present a wideband architecture for modula- tors using a single active stage and two switched capacitor passive stages The mixed active-passive implementation has performance advantages over traditional switched-capacitor (SC) or contin- uous-time implementations, particularly for high-resolution, wideband applications with high sampling rates and moderate oversampling ratios Design insensitivity to clock jitter and process variations is achieved by the good choice of the modulator archi- tecture The proposed modulator is designed in 013- m CMOS technology and meets all major requirements for application in IEEE 80216 wireless MAN receivers Circuit simulations show that the modulator with a single bit quantizer consumes 55 mW from a 12-V power supply and achieves a 9-bit resolution over a 10-MHz bandwidth at an OSR of Good performance is also achieved for lower bandwidth applications Index Terms—Analog-to-digital (A/D) converter (ADC), delta-sigma, passive, receiver, switched capacitor (SC), wideband
22 citations
01 Dec 2010
TL;DR: An optimization method for minimization of quantization noise in ΣΔ-based RF transmitters to enable the use of reconstruction filters with wider passband, or alternatively, a lower switch-rate to improve the transmitter efficiency.
Abstract: This paper describes an optimization method for minimization of quantization noise in ΣΔ-based RF transmitters. The aim of the method is to enable the use of reconstruction filters with wider passband, or alternatively, a lower switch-rate. The method uses a general representation of the ΣΔ converters in combination with a differentiable approximation of the quantizer. Based on this, a Monte Carlo-based algorithm is developed around the damped Gauss-Newton iteration. As a result of the suggested algorithm, the residual quantization noise after reconstruction filtering is significantly decreased. Finally, simulations using a bandlimited signal with a Gaussian distribution are used to demonstrate the capabilities of the suggested algorithm when applied with the proposed ΣΔ modulator representation. The resulting performance is compared to several cases of ΣΔ converters designed using traditional methods, demonstrating significant improvements in terms of reduced reconstruction normalized mean square error. This implies that the transmitter efficiency can be improved with minor changes in the modulator implementation.
22 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...The simulations evaluating the final results are put in terms of reconstructed , since this is the most common figure of merit throughout the literature [26]....
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...Generally, is required for a stable 1-bit modulator [26], [29]....
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...Both of these implementations are described in [26]....
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...The NTFs of these modulators has been optimized using the toolbox [28], described in detail in [26]....
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01 Mar 2013
TL;DR: In these experiments, the single-bit filters using ternary coefficients were found to dissipate less power compared to the conventional approach despite their need to operate at much higher clock rates and offer useful area savings at lower filter orders.
Abstract: While one-bit ΣΔ modulators are widely used in Analog to Digital conversion stages due to their inherent linearity and precision, it is less common for the entire digital processing path to operate in single bit mode at the oversampled rate of the conversion system. The conventional approach has been to decimate the signal bit stream after conversion and for the remaining processing to be performed in standard multi-bit binary at the Nyquist rate and with a resolution mandated by the dynamic range and noise. Using a Finite Impulse Response filter design as an example, we compare the area and performance of this conventional approach with the alternative single bit approach that operates directly on the ΣΔ data stream using ternary coefficients {?1, 0, +1} derived from the ΣΔ modulation of the target impulse response. Filters exhibiting approximately equivalent spectral performance in the two alternative approaches were developed using VHDL and simulated using some commercial FPGA types. In these experiments, the single-bit filters using ternary coefficients were found to dissipate less power compared to the conventional approach despite their need to operate at much higher clock rates. They also exhibit up to 40% higher performance and offer useful area savings at lower filter orders. At higher orders, the ΣΔ approach retains its power and performance advantages but exhibits slightly higher chip area. The simplicity and low power of the ΣΔ approach makes it applicable to mobile communication processing using low cost FPGA technology.
22 citations
References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations