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Understanding Delta-Sigma Data Converters

TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
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Journal ArticleDOI
TL;DR: This paper presents a delta-sigma modulation (DSM) control scheme for noninverting buck–boost (NIBB) converter that features a duobinary encoding for four power switch controls and achieves high conversion efficiency.
Abstract: This paper presents a delta-sigma modulation (DSM) control scheme for noninverting buck–boost (NIBB) converter that features a duobinary encoding for four power switch controls. The proposed scheme converts the single-bit output of the modulator into a 1.5-b signal to enable a three-phase operation comprising the charging, bypassing, and discharging phases. This control method reduces both switching and conduction losses by changing only two switches in each period, thus, achieving high conversion efficiency. A smooth mode transition is provided by the DSM controller, which automatically and continuously determines the operating mode of the converter. Thus, the dead zone can be effectively released with improved transient responses. Furthermore, the spurious tones in the output are effectively eliminated by the robust noise shaping capability of the modulator. The proposed DSM-based NIBB converter was implemented on a 180-nm CMOS. It regulated the output in the range of 2.0–4.6 V with input voltage of 2.5–5.0 V, and the maximal load current was 500 mA. The converter showed a peak efficiency of 94.8% at 90-mA load and the output voltage ripples were maintained under 18 mV. A low noise floor with the first spurious peak located –92 dBc below the signal was achieved across all mode operations. In addition, the converter occupied a small chip area of 1.51 mm2.

18 citations


Cites background or methods from "Understanding Delta-Sigma Data Conv..."

  • ...DSM, the modulator accurately estimates the input signal by averaging a number of samples even though the instantaneous output is very coarse [21]....

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  • ...can be used to evaluate how the DSM affects the signal response from its input to the output [21]....

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Proceedings ArticleDOI
18 Jan 2009
TL;DR: In this paper, a novel modulation concept based on Δ-Σ modulation dedicated for a Class-S Amplifier based on GaN technology is presented, including system considerations of efficient modulation schemes for GaN switching transistors, which suffer from many limits.
Abstract: A novel modulation concept based on Δ-Σ modulation dedicated for a Class-S Amplifier based on GaN technology is presented. This paper includes system considerations of efficient modulation schemes for GaN switching transistors, which suffer from many limits. The analyses are focused on evaluating the impact of modulation scheme on the switching conditions of the transistors. Moreover practical figures of merits are introduced for defining optimum modulation strategy. Simulations are performed for a carrier frequency of 890.88 MHz for UMTS 5 MHz bandwidth signal. Results describe the main differences and limits of modulation schemes dedicated for switching mode power amplifiers.

18 citations

Journal ArticleDOI
Liang Qi1, Sai-Weng Sin1, Seng-Pan U1, Franco Maloberti1, Rui P. Martins1 
TL;DR: A discrete time 2-1 MASH Delta-Sigma modulator with multirate opamp sharing for analog-to-digital converters, targeting the optimization of power efficiency in active blocks, such as opamps and quantizers, is presented.
Abstract: This paper presents a discrete time 2-1 MASH Delta-Sigma ( $\Delta \Sigma )$ modulator with multirate opamp sharing for analog-to-digital converters, targeting the optimization of power efficiency in active blocks, such as opamps and quantizers. Through the allocation of different settling times to the opamps and by adopting the multirate technique, the power of the shared opamps is utilized more efficiently, and the 4-b successive approximation register quantizer and the data weighted averaging block in the first stage enjoy additional operation time. Moreover, a detailed analysis and related simulations are presented to validate the enhanced opamp power efficiency in the proposed sharing scheme. The 65-nm CMOS experimental chip running at multirate 120/240 MHz achieves a mean signal-to-noise and distortion ratio (SNDR) of 77.1 dB for a 5-MHz bandwidth, consuming 4.2 mW from a 1.2 V supply and occupying 0.066-mm2 core area. It exhibits a Walden figure of merit (FoM) of 69.7 fJ/conv-step and a Schreier FoM of 167.9 dB based on SNDR.

18 citations


Cites background or methods from "Understanding Delta-Sigma Data Conv..."

  • ...The out-of-band gain needs to be reduced to stabilize the high-order modulator at the expense of increasing quantization noise as well as the circuit complexity owing to additional coefficient paths [2]....

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  • ...Moreover, due to the feedforward and oversampling properties, the signal transfer function (STF) of the first loop approximates unity....

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  • ...However, the perfect matching between analog and digital transfer functions in MASH modulators is highly required to eliminate the quantization noise of the preceding stages, otherwise the noise leakage will deteriorate the overall performance significantly [2]....

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  • ...enormous as in audio-bandwidth applications (a large OSR employed) [2]....

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  • ...Then, C(z) can be approximately expressed as, C(z) ≈ 1 − (ε1 + ε2 + εa) (34) Combining (31) and (34), NTF1(z) will become, NT F1(z) ≈ (1 − z −1)2 1 − (ε1 + ε2 + εa) ≈ [1 + (ε1 + ε2 + εa)](1 − z−1)2 (35) Also, combining (27) and (35), STF1(z) can be calculated as, ST F1(z) = Ls1(z) 1 − Ln1(z) = B(z) (1 − z−1)2 · [1 + (ε1 + ε2 + εa)](1−z −1)2 = [1 + (ε1 + ε2 + εa)] · B(z) (36) Ignoring the last two terms with high pass filtering of B(z) in (30) within band of interest, then STF1(z) becomes, ST F1(z) = [1 − (ε1 + ε2 + εa)2]z−1 ≈ z−1 (37) As a result, Y1(z) can be finally approximated by, Y1(z) ≈ z−1 X (z) + (1 + ε1st)(1 − z−1)2 E1(z) ε1st = ε1 + ε2 + εa (38)...

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Journal ArticleDOI
TL;DR: A new third-order continuous-time time-to-digital converter (TDC) is proposed that shapes quantization noise so that the TDC quantization Noise no longer determines the in-band phase noise of a digital PLL.
Abstract: Frequency-modulated continuous-wave (FMCW) radar requires low in-band phase noise, fast-settling high-frequency phase-locked loops (PLLs). We propose a new third-order continuous-time time-to-digital converter (TDC) that shapes quantization noise so that the TDC quantization noise no longer determines the in-band phase noise of a digital PLL. The new TDC allows a digital PLL to have an in-band phase noise performance similar to that of an analog PLL. Prototype 30- and 40-GHz PLLs, fabricated in 65-nm CMOS as sources for a 240-GHz scanning FMCW radar, consume 34.8 and 40 mW, respectively. The 30-GHz prototype PLL has a normalized phase noise of −213 dBc/Hz2 (at 100-kHz offset) and an FoMJitter of −230 dB (from 10 kHz to 1 MHz), thanks to the measured 182 fs integrated rms noise of TDC.

17 citations


Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...9) is much less susceptible to limit cycles, which would create distortion in the modulator output and limit dynamic range [29]....

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  • ...For a first-order CT modulator [28], [29], the STF and NTF are STF = 1 − z −1 s and NTF = 1 − z−1 where z = es ....

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Journal ArticleDOI
TL;DR: A fifth-order modulator is designed to convert audio-band signals with an effective resolution of 20 bits to demonstrate the effectiveness of the proposed analysis and method of design.
Abstract: Single-bit sigma-delta modulators operated in the quasi-sliding mode are investigated. Sufficient conditions for the existence and stability of this mode of operation are derived. The derived stability conditions, along with an accurate prediction of its performance, enable a high-order modulator to be exactly designed. A fifth-order modulator is designed to convert audio-band signals with an effective resolution of 20 bits to demonstrate the effectiveness of the proposed analysis and method of design.

17 citations

References
More filters
Journal ArticleDOI
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

399 citations

Journal ArticleDOI
James C. Candy1
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.

342 citations

Journal ArticleDOI
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

284 citations

Book ChapterDOI
James C. Candy1, O. Benjamin1
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.

255 citations

Journal ArticleDOI
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >

211 citations