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Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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TL;DR: An $8\times $ -oversampling successive approximation register (SAR) analog-to-digital converter (ADC) with configurable center frequency of noise shaping (NS), which permits the signal passband being configured to any one of the 8 equally divided sub-bands in the first Nyquist band.
Abstract: This article presents an $8\times $ -oversampling successive approximation register (SAR) analog-to-digital converter (ADC) with configurable center frequency of noise shaping (NS), which permits the signal passband being configured to any one of the 8 equally divided sub-bands in the first Nyquist band. The configurable noise shaping is realized by an error-feedback (EF) structure with an adjustable 2-tap switched-capacitor (SC) FIR filter. Taking advantage of the sub-bands’ symmetry, the selection of the 8 sub-bands are determined by only a 2-bit controlled variable capacitor in the FIR filter in addition to one bit indicating which half-band the target sub-band is in. As a result, the configuration circuit is area efficient and introduces very little parasitic into the critical EF path. A 2-stage clock-controlled amplifier (CAMP) is proposed for the EF path, which can ensure gain and speed simultaneously through allocating reasonable currents into the gain stage and the driving stage separately. Implemented in 65-nm CMOS process, measurement results under a sampling rate of 10 MSPS show that the prototype achieves signal-to-noise-and-distortion (SNDR) of 71.9~74.6 dB in the 8 sub-bands with 625-KHz bandwidth, corresponding to a Scherier FoM of 171.4 -174 dB. The ADC prototype occupies 0.03-mm2 core area and consumes 70- $\mu \text{W}$ average power at 1-V supply voltage.
15 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...The error-feedback (EF) structure is also effective to form an NS SAR ADC [24], [25], which has been further combined with pipelined structure to improve the...
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...In NS SAR ADC, the SAR ADC core usually provides multi-bit quantization, which solves the stability problem of conventional high-order sigmadelta modulator with a coarse quantizer to a large extent, meaning that high-order NTF can be employed safely [24]....
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...Based on the EF structure in [24], the FIR filter is realized as a SC network including a 2-stage CAMP, as that shown in Fig....
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01 Jan 2010
TL;DR: In this paper, the authors present integrated circuits for the realization of interface electronics for capacitive MEMS (microelectro-mechanical system) inertial sensors, i.e. accelerometers and gyroscopes.
Abstract: This thesis is composed of 13 publications and an overview of the research topic, which also summarizes the work. The research presented in this thesis concentrates on integrated circuits for the realization of interface electronics for capacitive MEMS (micro-electro-mechanical system) inertial sensors, i.e. accelerometers and gyroscopes. The research focuses on circuit techniques for capacitive detection and actuation and on high-voltage and clock generation within the sensor interface. Characteristics of capacitive accelerometers and gyroscopes and the electronic circuits for accessing the capacitive information in open- and closed-loop configurations are introduced in the thesis. One part of the experimental work, an accelerometer, is realized as a continuous-time closed-loop sensor, and is capable of achieving sub-micro-g resolution. The interface electronics is implemented in a 0.7-µm high-voltage technology. It consists of a force feedback loop, clock generation circuits, and a digitizer. Another part of the experimental work, an analog 2-axis gyroscope, is optimized not only for noise, but predominantly for low power consumption and a small chip area. The implementation includes a pseudo-continuous-time sense readout, analog continuous-time drive loop, phase-locked loop (PLL) for clock generation, and high-voltage circuits for electrostatic excitation and high-voltage detection. The interface is implemented in a 0.35-µm high-voltage technology within an active area of 2.5 mm². The gyroscope achieves a spot noise of 0.015 °/s/√Hz for the x-axis and 0.041 °/s/√Hz for the y-axis. Coherent demodulation and discrete-time signal processing are often an important part of the sensors and also typical examples that require clock signals. Thus, clock generation within the sensor interfaces is also reviewed. The related experimental work includes two integrated charge pump PLLs, which are optimized for compact realization but also considered with regard to their noise performance. Finally, this thesis discusses fully integrated high-voltage generation, which allows a higher electrostatic force and signal current in capacitive sensors. Open- and closed-loop Dickson charge pumps and high-voltage amplifiers have been realized fully on-chip, with the focus being on optimizing the chip area and on generating precise spurious free high-voltage signals up to 27 V.
15 citations
TL;DR: In this article, the authors propose adaptive and multi-level adaptive sampling models as alternatives to conventional LC schemes and apply an iterative algorithm to improve the reconstruction quality of LC A/D converters.
Abstract: Level-crossing (LC) analog-to-digital (A/D) converters can efficiently sample certain classes of signals. An LC A/D converter is a real-time asynchronous system, which encodes the information of an analog signal into a sequence of non-uniformly spaced time instants. In particular, this class of A/D converters uses an asynchronous data conversion approach, which is a power efficient technique. In this study, the authors propose adaptive and multi-level adaptive LC sampling models as alternatives to conventional LC schemes and apply an iterative algorithm to improve the reconstruction quality of LC A/D converters. This simulation results show that multi-level adaptive LC outperforms conventional A/D converters such as sigma-delta A/D converters in terms of performance and computational complexity.
15 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...The over-sampled signal will be then downsampled at the last stage of A/D conversion [3, 4]....
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04 Oct 2010
TL;DR: Two new EPWM architectures called the envelope subtraction EPWM (ES-EPWM) and the amplitude compensated EP WM (AC-EP WM) are proposed to enhance quantization noise suppression.
Abstract: The envelope pulse-width modulation (EPWM) transmitter has been proposed to address the issue of low power efficiency in the linear amplification of multicarrier signals such as the OFDM. However, the delta-sigma (Σ-Δ) modulator in the EPWM transmitter generates quantization noise that degrades signal quality. In this paper, two new EPWM architectures called the envelope subtraction EPWM (ES-EPWM) and the amplitude compensated EPWM (AC-EPWM) are proposed to enhance quantization noise suppression. The architectures generate a narrowband noise-canceling signal that is either subtracted to the PWM envelope signal (ES-EPWM) or multiplied to the PM signal (AC-EPWM). Using the IEEE 802.11a OFDM signal, simulations were done with varying canceling signal bandwidth and oversampling ratio (OSR). Results showed that increasing the canceling signal bandwidth improved the performance of the ES-EPWM transmitter in terms of the measured error vector magnitude (EVM) and adjacent channel leakage power ratio (ACLR). A similar behavior was observed for the AC-EPWM transmitter, but only up to a certain canceling signal bandwidth. For an OSR of 32 and a canceling signal bandwidth of 40MHz, both ES-EPWM and AC-EPWM transmitters were able to improve the ACLR by 6 dB and reduce the EVM to 2/3.
15 citations
TL;DR: In this paper, a CMOS digitized silicon condenser microphone for acoustic applications is proposed, which is suitable for mobile phones, laptops, PDAs, and hearing aids, etc.
Abstract: In this paper, a CMOS digitized silicon condenser microphone for acoustic applications is newly proposed. The proposed CMOS digitized silicon condenser microphone is attractive due to the fact that the sensor and all the circuits are robustly and compactly integrated. Another innovation of this proposed CMOS digitized silicon condenser microphone is that it could be operated without charge pump circuits. Thus, the sensor and circuits can be performed at the same power supply. Based upon 0.35 μ m 2P4M CMOS technology with 3 V power supply, measurement results have successfully verified the correct function and performance of the proposed CMOS digitized silicon condenser microphone. The area of the proposed CMOS digitized silicon condenser microphone is 1444 × 1383 μm2 and the FOM of the sigma-delta modulator is 163.85 dB. The proposed CMOS digitized silicon condenser microphone is suitable for mobile phones, laptops, PDAs, and hearing aids, etc.
15 citations
Additional excerpts
...In order to consider the degradation of the achievable DR [11] and circuit nonidealities, an OSR of 128 and of 4 are chosen....
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References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations