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Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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TL;DR: System-level simulations of the finite impulse response DAC-based architecture show that the requirements of the standards can be met with maximum hardware sharing and reduced area penalty.
Abstract: IEEE 802.11ac (WiFi) and IEEE 802.11ad (60-GHz WiGig) are emerging gigabit-per-second standards providing complementary services but different nature of signals. The 802.11ac targets high-resolution and narrow-to-medium bandwidth channels, while 802.11ad aims to provide broadband communications with simple modulation schemes. This work proposes a single-physical-layer transmitter baseband architecture for both 11ac and 11ad standards. The core of the proposed transmitter is a configurable mixed-signal digital-to-analog converter (DAC), which has an embedded semidigital filtering tailored for four WiFi modes (20, 40, 80, and 160 MHz) and the 1.76-GHz bandwidth of the 60-GHz WiGig standard. The DAC operates on the oversampled WiFi and raw WiGig data at a common 3.52-GHz clock frequency. System-level simulations of the finite impulse response DAC-based architecture show that the requirements of the standards can be met with maximum hardware sharing and reduced area penalty.
15 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...feedback (CRFB) topology of the Schreier Toolbox [10]....
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...The required coefficients of the filters are generated using functions from the Schreier Toolbox [10]....
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...This modulator uses the cascade of resonators with feedback (CRFB) topology of the Schreier Toolbox [10]....
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TL;DR: The design of a MGy radiation tolerant 16 bit resolver-to-digital converter (RDC) in 130 nm CMOS technology is presented, able to operate under temperatures up to 125 °C, and to allow multiplexing with signals from other conventional sensors for compact, robust read-out architectures.
14 citations
TL;DR: This paper describes a high-speed delta-sigma modulator with 65-nm CMOS technology for ultrasound imaging systems based on a 4th-order single-loop switched-capacitor architecture with a 4-bit quantizer, which eliminates the extra power consumption and silicon area required by the adder.
Abstract: This paper describes a high-speed delta-sigma modulator with 65-nm CMOS technology for ultrasound imaging systems. The delta-sigma modulator is based on a 4th-order single-loop switched-capacitor architecture with a 4-bit quantizer. The designed modulator has the advantages associated with input-feedforward architecture, such as the reduced output swing of the integrator, which relaxes the amplifiers' design requirements. Due to the power and area overheads and the timing constraint of the active adder in the conventional multibit input-feedforward modulator, we use an adder-less input-feedforward delta-sigma architecture. As a result, the designed architecture eliminates the extra power consumption and silicon area required by the adder. The designed architecture also relaxes the timing requirement for the quantizer and the dynamic element-matching block compared with the conventional delta-sigma modulator. The modulator achieves a dynamic range of 76dB and a peak signal-to-noise-plus-distortion ratio of 72.3 dB in a signal bandwidth of 6 MHz. The power consumption is 18.5 mW with 1.2-V supply voltage, and the chip core size is 0.25 mm2. The energy required per conversion step is 0.46 pJ/conv.
14 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...The effective load capacitance is computed by considering the parasitic component [21], [33]....
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...5, because loop stability is improved in this modulator and this brings about increased SNRs [24], [33], [36]....
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TL;DR: A new asynchronous high speed multi-modulus divider (MMD) architecture that significantly reduces the delay of the critical path, which not only pushes to ultra-high speed operation, but also allows retiming techniques to suppress jitter accumulation from the divider chain simultaneously.
Abstract: A new asynchronous high speed multi-modulus divider (MMD) architecture is presented in this letter. This new architecture significantly reduces the delay of the critical path, which not only pushes to ultra-high speed operation, but also allows retiming techniques to suppress jitter accumulation from the divider chain simultaneously. A prototype in a 65 nm CMOS technology has demonstrated an improved speed over three times compared with a conventional MMD and a reduced phase noise about 8.4 dB due to a retiming scheme. To the authors' best knowledge, this MMD has demonstrated to date the highest operating frequency static MMD with retiming function in CMOS. Due to its static implementation, this MMD can operate from 19 GHz down to close to dc with programmable division ratios from 16 to 31. This MMD consumes 39.8 mW power and occupies 0.011 mm2 chip area.
14 citations
TL;DR: It is shown that in a MASH ADC, FIR feedback has the additional benefit of filtering the error waveform of the first stage that is fed into the second stage, and the principle is applied to an audio continuous-time delta–sigma modulator.
Abstract: We combine a first-order single-bit CT $\Delta \!\Sigma \text{M}$ employing finite impulse-response (FIR) feedback with a 1-bit second-order $\Delta \Sigma $ back end to achieve a modulator with maximum stable amplitude (MSA) that is close to full scale, and a third-order overall noise transfer function (NTF). FIR feedback is used in the input stage to reduce clock-jitter sensitivity, improve linearity, and reduce chopping artifacts. We show that in a MASH ADC, FIR feedback has the additional benefit of filtering the error waveform of the first stage that is fed into the second stage. We apply the principle to an audio continuous-time delta–sigma modulator. A prototype chip, fabricated in 180-nm CMOS to demonstrate the principle, achieves 100.9-dB SNDR in a 24-kHz bandwidth and dissipates 265 $\mu \text{W}$ . The resulting Schreier figure of merit is 180.5 dB.
14 citations
References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations