Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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26 Aug 2011
TL;DR: The experimental validation has proved that it is possible to measure rms values of sinusoidal signals with 1 V peak amplitudes for frequencies up to 1.3 kHz with uncertainty of 8 μV/V, significantly improving the uncertainty achievable with de facto standard which reaches 8 μv/V at 500 Hz.
Abstract: A sampling system based on a 24-bits sigma-delta analog-to-digital converter (ADC) was built and characterized in order to study the feasibility of using this type of ADCs in electrical metrology.
The non-linearities of the sampling system have been studied and a model for postcorrecting the measured data points established. The Hammerstein model, consisting of a static non-linear part and a linear system, was employed. A 4-th order polynomial accounts for the non-linearities of the analog electronics and the input stages of the sigma delta ADC. The linear part corresponds to the transfer function of the decimation filters internal to the ADC. The parameters for the model of the system were determined using noiseless and drift-free waveforms from a Josephson waveform synthesizer.
The performance of the sampling system was verified experimentally by comparing the measured root-mean-square (rms) value of sinusoidal signals with the results from an established method. The results obtained using the post-corrected samples from the sampling system at 125 Hz agreed to within 2 μV/V with the de facto standard in metrology laboratories, which uses a high accuracy digital voltmeter.
Precision measurements are limited by the decimation filters inside the ADC and can
only be carried out for frequencies below 1/24-th of the equivalent sampling rate. The characterization results have shown that the non-linearities have been compensated to 5 μV/V or better and the effective resolution exceeds 20 bits, over an input range of 1 V at the equivalent sampling rate of 32 kHz. The experimental validation has proved that it is possible to measure rms values of sinusoidal signals with 1 V peak amplitudes for frequencies up to 1.3 kHz with uncertainty of 8 μV/V, significantly improving the uncertainty achievable with de facto standard which reaches 8 μV/V at 500 Hz.
14 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...Oversampling converters offer several advantages over Nyquist-rate converters such as relaxation on the anti-aliasing filter design, high resolution, low non-linearity and quantization noise shaping [4, 18]....
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...The internal structure of a Σ-∆ ADC includes an analog part, which consists of a modulator or a cascade of modulators (in a multistage topology) and a digital part with a quantizer and several digital decimation filters [4]....
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...4 Other Second Order Structures Other structures for a second order modulator exist [4]....
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...general expression to represent the modulator model is [4]:...
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...Sigma-Delta analog-to-digital converters (Σ-∆ ADC) have recently become more attractive for high precision sampling applications due to their improved low-noise characteristics, high resolution and low non-linearity [4]....
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TL;DR: In this article, a design flow for ΔΣ modulators is illustrated, allowing quantization noise to be shaped according to an arbitrary weighting profile, and the flow is best suited for digital architectures.
Abstract: A design flow for ΔΣ modulators is illustrated, allowing quantization noise to be shaped according to an arbitrary weighting profile. Based on finite-impulse-response noise transfer functions, possibly with high order, the flow is best suited for digital architectures. This work builds on a recent proposal in which the modulator is matched to the reconstruction filter, showing that this type of optimization can benefit a wide range of applications in which noise (including in-band noise) is known to have a different impact at different frequencies. The designs of a multiband modulator, a modulator avoiding dc noise, and an audio modulator capable of distributing quantization artifacts according to a psychoacoustic model are discussed as examples. A software toolbox is provided as a general design aid and to replicate the proposed results.
14 citations
TL;DR: A programmable noise-shaped post-mixer gain-filtering circuit for a CMOS Mobile-TV tuner relax the noise-linearity tradeoff in the receiver chain by providing blocker rejection following the mixer outputs.
Abstract: In this paper, a new technique for realizing area-efficient, low-noise filters is introduced. The proposed filter topologies utilize noise shaping techniques to shift the noise of the passive and active filter components out of the passband of the filter. This is illustrated by implementing a programmable noise-shaped post-mixer gain-filtering circuit for a CMOS Mobile-TV tuner. The proposed circuits relax the noise-linearity tradeoff in the receiver chain by providing blocker rejection following the mixer outputs. The filter provides an in-band input referred noise density as low as 7.5 nV/sqrt(Hz). The measured out-of-band IIP3 values are 30 dBV and 31.5 dBV for the 3.8-MHz (DVB-H) and 750-kHz (ISDB-T) modes, respectively. Total current consumption is 5.5 mA from a 1.2-V supply. The gain of the block is programmable to be 0 dB, 8ndB, 14 dB, or 20 dB. The design occupies a die area of 0.28 mm2 in a 65-nm CMOS process covering a frequency band of 700 kHz to 5.2 MHz as a universal mobile-TV integrated baseband gain-filtering solution.
14 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...One advantage of CT-SD converters is that it provides inherent anti-aliasing filtering [23]....
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07 Jun 2009
TL;DR: In this paper, the authors studied the unwanted spectral components that arise when baseband polar signals are upconverted to RF using pulse width modulation and pulse position modulation (PPM) in sigma delta based modulators.
Abstract: Existing 3G base stations require high efficiency linear radio frequency (RF) power amplifiers (PAs). Switch Mode PAs can have improved efficiency but require a pulse train as a drive signal. This paper studies the unwanted spectral components that arise when baseband polar signals are upconverted to RF using pulse width modulation and pulse position modulation (PPM) in sigma delta based modulators. The dominant distortions are shown to be third order and image components generated in the PPM circuit. In a single carrier environment, an increase in offset frequency increases the unwanted spectral components. Offsets less than 10 MHz are required to keep unwanted components 40 dB below the signal level Also, the effect of distortions on adjacent channel powers is quantified using an OFDM input signal.
14 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...2 shows the block diagram of polar Σ∆ which consists of two second-order lowpass Σ∆s (MOD 2) [7], amplitude and phase quantisers and a ‘polar to PWM/PPM’ block....
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TL;DR: A 50 MS/s two-step flash-MASH 1-1-1 time-to-digital converter employing a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizes an error-feedback topology.
Abstract: A 50 MS/s two-step flash-MASH 1-1-1 time-to-digital converter (TDC) employing a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizes an error-feedback topology. Such an error-feedback unit of 1st-order noise-shaping TDC can be cascaded as a multi-stage noise shaping (MASH) configuration to achieve higher-order noise-shaping and, thereby high resolution. This paper also discusses different noise sources, linearity and noise tradeoffs in noise-shaping TDC and then demonstrates a histogram testing technique to correct the mismatch of 1st stage flash TDC. An on/off-chip delay modulation (DM) measurement technique is presented to characterize the TDC linearity and noise performance. Fabricated in 40-nm CMOS technology, the proposed TDC consumes 1.32 mW from a 1.1 V supply. At frequency below 2.5 MHz, the TDC error integrates to 147fsrms, which is equal to equivalent flash resolution of 1.6 ps.
14 citations
Cites methods from "Understanding Delta-Sigma Data Conv..."
...Next, the residue is finely quantized by the 2nd stage MASH 1-1-1 noise-shaping converter, which is configured by cascading three 1st-order EF modulators, which are free from stability concerns [37]....
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References
More filters
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations